Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d42c23d8ea6b1251022744d6e351d7ba161ace01 / . / arch / arm / dts / imx6qdl-sabresd.dtsi
blob: eddb3901745e7150450a246b57bf07295429d75b [file] [log] [blame]
Abel Vesaf4897e52019-02-01 16:40:16 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include <dt-bindings/clock/imx6qdl-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11 aliases {
12 mmc1 = &usdhc3;
13 };
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 memory@10000000 {
20 reg = <0x10000000 0x40000000>;
21 };
22
23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_usb_otg_vbus: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "usb_otg_vbus";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 gpio = <&gpio3 22 0>;
35 enable-active-high;
36 vin-supply = <&swbst_reg>;
37 };
38
39 reg_usb_h1_vbus: regulator@1 {
40 compatible = "regulator-fixed";
41 reg = <1>;
42 regulator-name = "usb_h1_vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 gpio = <&gpio1 29 0>;
46 enable-active-high;
47 vin-supply = <&swbst_reg>;
48 };
49
50 reg_audio: regulator@2 {
51 compatible = "regulator-fixed";
52 reg = <2>;
53 regulator-name = "wm8962-supply";
54 gpio = <&gpio4 10 0>;
55 enable-active-high;
56 };
57
58 reg_pcie: regulator@3 {
59 compatible = "regulator-fixed";
60 reg = <3>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_pcie_reg>;
63 regulator-name = "MPCIE_3V3";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 gpio = <&gpio3 19 0>;
67 enable-active-high;
68 };
69 };
70
71 gpio-keys {
72 compatible = "gpio-keys";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_keys>;
75
76 power {
77 label = "Power Button";
78 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
79 wakeup-source;
80 linux,code = <KEY_POWER>;
81 };
82
83 volume-up {
84 label = "Volume Up";
85 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
86 wakeup-source;
87 linux,code = <KEY_VOLUMEUP>;
88 };
89
90 volume-down {
91 label = "Volume Down";
92 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
93 wakeup-source;
94 linux,code = <KEY_VOLUMEDOWN>;
95 };
96 };
97
98 sound {
99 compatible = "fsl,imx6q-sabresd-wm8962",
100 "fsl,imx-audio-wm8962";
101 model = "wm8962-audio";
102 ssi-controller = <&ssi2>;
103 audio-codec = <&codec>;
104 audio-routing =
105 "Headphone Jack", "HPOUTL",
106 "Headphone Jack", "HPOUTR",
107 "Ext Spk", "SPKOUTL",
108 "Ext Spk", "SPKOUTR",
109 "AMIC", "MICBIAS",
110 "IN3R", "AMIC";
111 mux-int-port = <2>;
112 mux-ext-port = <3>;
113 };
114
115 backlight_lvds: backlight-lvds {
116 compatible = "pwm-backlight";
117 pwms = <&pwm1 0 5000000>;
118 brightness-levels = <0 4 8 16 32 64 128 255>;
119 default-brightness-level = <7>;
120 status = "okay";
121 };
122
123 leds {
124 compatible = "gpio-leds";
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_gpio_leds>;
127
128 red {
129 gpios = <&gpio1 2 0>;
130 default-state = "on";
131 };
132 };
133
134 panel {
135 compatible = "hannstar,hsd100pxn1";
136 backlight = <&backlight_lvds>;
137
138 port {
139 panel_in: endpoint {
140 remote-endpoint = <&lvds0_out>;
141 };
142 };
143 };
144};
145
146&ipu1_csi0_from_ipu1_csi0_mux {
147 bus-width = <8>;
148 data-shift = <12>; /* Lines 19:12 used */
149 hsync-active = <1>;
150 vsync-active = <1>;
151};
152
153&ipu1_csi0_mux_from_parallel_sensor {
154 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
155};
156
157&ipu1_csi0 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_ipu1_csi0>;
160};
161
162&mipi_csi {
163 status = "okay";
164
165 port@0 {
166 reg = <0>;
167
168 mipi_csi2_in: endpoint {
169 remote-endpoint = <&ov5640_to_mipi_csi2>;
170 clock-lanes = <0>;
171 data-lanes = <1 2>;
172 };
173 };
174};
175
176&audmux {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_audmux>;
179 status = "okay";
180};
181
182&clks {
183 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
184 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
185 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
186 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
187};
188
189&ecspi1 {
190 cs-gpios = <&gpio4 9 0>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_ecspi1>;
193 status = "okay";
194
195 flash: m25p80@0 {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 compatible = "st,m25p32", "jedec,spi-nor";
199 spi-max-frequency = <20000000>;
200 reg = <0>;
201 };
202};
203
204&fec {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_enet>;
Fabio Estevamd42c23d2020-06-17 14:33:16 -0300[diff] [blame^]207 phy-mode = "rgmii-id";
Abel Vesaf4897e52019-02-01 16:40:16 +0000[diff] [blame]208 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
209 status = "okay";
210};
211
212&hdmi {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_hdmi_cec>;
215 ddc-i2c-bus = <&i2c2>;
216 status = "okay";
217};
218
219&i2c1 {
220 clock-frequency = <100000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c1>;
223 status = "okay";
224
225 codec: wm8962@1a {
226 compatible = "wlf,wm8962";
227 reg = <0x1a>;
228 clocks = <&clks IMX6QDL_CLK_CKO>;
229 DCVDD-supply = <&reg_audio>;
230 DBVDD-supply = <&reg_audio>;
231 AVDD-supply = <&reg_audio>;
232 CPVDD-supply = <&reg_audio>;
233 MICVDD-supply = <&reg_audio>;
234 PLLVDD-supply = <&reg_audio>;
235 SPKVDD1-supply = <&reg_audio>;
236 SPKVDD2-supply = <&reg_audio>;
237 gpio-cfg = <
238 0x0000 /* 0:Default */
239 0x0000 /* 1:Default */
240 0x0013 /* 2:FN_DMICCLK */
241 0x0000 /* 3:Default */
242 0x8014 /* 4:FN_DMICCDAT */
243 0x0000 /* 5:Default */
244 >;
245 };
246
247 ov5642: camera@3c {
248 compatible = "ovti,ov5642";
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_ov5642>;
251 clocks = <&clks IMX6QDL_CLK_CKO>;
252 clock-names = "xclk";
253 reg = <0x3c>;
254 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
255 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
256 rev B board is VGEN5 */
257 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
258 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
259 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
260 status = "disabled";
261
262 port {
263 ov5642_to_ipu1_csi0_mux: endpoint {
264 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
265 bus-width = <8>;
266 hsync-active = <1>;
267 vsync-active = <1>;
268 };
269 };
270 };
271};
272
273&i2c2 {
274 clock-frequency = <100000>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_i2c2>;
277 status = "okay";
278
279 ov5640: camera@3c {
280 compatible = "ovti,ov5640";
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_ov5640>;
283 reg = <0x3c>;
284 clocks = <&clks IMX6QDL_CLK_CKO>;
285 clock-names = "xclk";
286 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
287 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
288 rev B board is VGEN5 */
289 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
290 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
291 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
292
293 port {
294 ov5640_to_mipi_csi2: endpoint {
295 remote-endpoint = <&mipi_csi2_in>;
296 clock-lanes = <0>;
297 data-lanes = <1 2>;
298 };
299 };
300 };
301
302 pmic: pfuze100@8 {
303 compatible = "fsl,pfuze100";
304 reg = <0x08>;
305
306 regulators {
307 sw1a_reg: sw1ab {
308 regulator-min-microvolt = <300000>;
309 regulator-max-microvolt = <1875000>;
310 regulator-boot-on;
311 regulator-always-on;
312 regulator-ramp-delay = <6250>;
313 };
314
315 sw1c_reg: sw1c {
316 regulator-min-microvolt = <300000>;
317 regulator-max-microvolt = <1875000>;
318 regulator-boot-on;
319 regulator-always-on;
320 regulator-ramp-delay = <6250>;
321 };
322
323 sw2_reg: sw2 {
324 regulator-min-microvolt = <800000>;
325 regulator-max-microvolt = <3300000>;
326 regulator-boot-on;
327 regulator-always-on;
328 regulator-ramp-delay = <6250>;
329 };
330
331 sw3a_reg: sw3a {
332 regulator-min-microvolt = <400000>;
333 regulator-max-microvolt = <1975000>;
334 regulator-boot-on;
335 regulator-always-on;
336 };
337
338 sw3b_reg: sw3b {
339 regulator-min-microvolt = <400000>;
340 regulator-max-microvolt = <1975000>;
341 regulator-boot-on;
342 regulator-always-on;
343 };
344
345 sw4_reg: sw4 {
346 regulator-min-microvolt = <800000>;
347 regulator-max-microvolt = <3300000>;
348 regulator-always-on;
349 };
350
351 swbst_reg: swbst {
352 regulator-min-microvolt = <5000000>;
353 regulator-max-microvolt = <5150000>;
354 };
355
356 snvs_reg: vsnvs {
357 regulator-min-microvolt = <1000000>;
358 regulator-max-microvolt = <3000000>;
359 regulator-boot-on;
360 regulator-always-on;
361 };
362
363 vref_reg: vrefddr {
364 regulator-boot-on;
365 regulator-always-on;
366 };
367
368 vgen1_reg: vgen1 {
369 regulator-min-microvolt = <800000>;
370 regulator-max-microvolt = <1550000>;
371 };
372
373 vgen2_reg: vgen2 {
374 regulator-min-microvolt = <800000>;
375 regulator-max-microvolt = <1550000>;
376 };
377
378 vgen3_reg: vgen3 {
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <3300000>;
381 };
382
383 vgen4_reg: vgen4 {
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <3300000>;
386 regulator-always-on;
387 };
388
389 vgen5_reg: vgen5 {
390 regulator-min-microvolt = <1800000>;
391 regulator-max-microvolt = <3300000>;
392 regulator-always-on;
393 };
394
395 vgen6_reg: vgen6 {
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <3300000>;
398 regulator-always-on;
399 };
400 };
401 };
402};
403
404&i2c3 {
405 clock-frequency = <100000>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_i2c3>;
408 status = "okay";
409
410 egalax_ts@4 {
411 compatible = "eeti,egalax_ts";
412 reg = <0x04>;
413 interrupt-parent = <&gpio6>;
414 interrupts = <7 2>;
415 wakeup-gpios = <&gpio6 7 0>;
416 };
417};
418
419&iomuxc {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_hog>;
422
423 imx6qdl-sabresd {
424 pinctrl_hog: hoggrp {
425 fsl,pins = <
426 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
427 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
428 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
429 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
430 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
431 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
432 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
433 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
434 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
435 >;
436 };
437
438 pinctrl_audmux: audmuxgrp {
439 fsl,pins = <
440 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
441 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
442 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
443 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
444 >;
445 };
446
447 pinctrl_ecspi1: ecspi1grp {
448 fsl,pins = <
449 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
450 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
451 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
452 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
453 >;
454 };
455
456 pinctrl_enet: enetgrp {
457 fsl,pins = <
458 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
459 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
460 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
461 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
462 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
463 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
464 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
465 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
466 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
467 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
468 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
469 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
470 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
471 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
472 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
473 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
474 >;
475 };
476
477 pinctrl_gpio_keys: gpio_keysgrp {
478 fsl,pins = <
479 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
480 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
481 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
482 >;
483 };
484
485 pinctrl_hdmi_cec: hdmicecgrp {
486 fsl,pins = <
487 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
488 >;
489 };
490
491 pinctrl_i2c1: i2c1grp {
492 fsl,pins = <
493 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
494 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
495 >;
496 };
497
498 pinctrl_i2c2: i2c2grp {
499 fsl,pins = <
500 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
501 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
502 >;
503 };
504
505 pinctrl_i2c3: i2c3grp {
506 fsl,pins = <
507 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
508 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
509 >;
510 };
511
512 pinctrl_ipu1_csi0: ipu1csi0grp {
513 fsl,pins = <
514 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
515 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
516 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
517 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
518 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
519 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
520 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
521 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
522 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
523 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
524 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
525 >;
526 };
527
528 pinctrl_ov5640: ov5640grp {
529 fsl,pins = <
530 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
531 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
532 >;
533 };
534
535 pinctrl_ov5642: ov5642grp {
536 fsl,pins = <
537 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
538 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
539 >;
540 };
541
542 pinctrl_pcie: pciegrp {
543 fsl,pins = <
544 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
545 >;
546 };
547
548 pinctrl_pcie_reg: pciereggrp {
549 fsl,pins = <
550 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
551 >;
552 };
553
554 pinctrl_pwm1: pwm1grp {
555 fsl,pins = <
556 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
557 >;
558 };
559
560 pinctrl_uart1: uart1grp {
561 fsl,pins = <
562 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
563 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
564 >;
565 };
566
567 pinctrl_usbotg: usbotggrp {
568 fsl,pins = <
569 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
570 >;
571 };
572
573 pinctrl_usdhc2: usdhc2grp {
574 fsl,pins = <
575 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
576 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
577 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
578 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
579 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
580 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
581 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
582 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
583 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
584 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
585 >;
586 };
587
588 pinctrl_usdhc3: usdhc3grp {
589 fsl,pins = <
590 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
591 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
592 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
593 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
594 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
595 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
596 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
597 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
598 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
599 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
600 >;
601 };
602
603 pinctrl_usdhc4: usdhc4grp {
604 fsl,pins = <
605 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
606 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
607 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
608 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
609 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
610 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
611 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
612 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
613 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
614 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
615 >;
616 };
617
618 pinctrl_wdog: wdoggrp {
619 fsl,pins = <
620 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
621 >;
622 };
623 };
624
625 gpio_leds {
626 pinctrl_gpio_leds: gpioledsgrp {
627 fsl,pins = <
628 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
629 >;
630 };
631 };
632};
633
634&ldb {
635 status = "okay";
636
637 lvds-channel@1 {
638 fsl,data-mapping = "spwg";
639 fsl,data-width = <18>;
640 status = "okay";
641
642 port@4 {
643 reg = <4>;
644
645 lvds0_out: endpoint {
646 remote-endpoint = <&panel_in>;
647 };
648 };
649 };
650};
651
652&pcie {
653 pinctrl-names = "default";
654 pinctrl-0 = <&pinctrl_pcie>;
655 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
656 vpcie-supply = <&reg_pcie>;
657 status = "okay";
658};
659
660&pwm1 {
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_pwm1>;
663 status = "okay";
664};
665
666&reg_arm {
667 vin-supply = <&sw1a_reg>;
668};
669
670&reg_pu {
671 vin-supply = <&sw1c_reg>;
672};
673
674&reg_soc {
675 vin-supply = <&sw1c_reg>;
676};
677
678&snvs_poweroff {
679 status = "okay";
680};
681
682&ssi2 {
683 status = "okay";
684};
685
686&uart1 {
687 pinctrl-names = "default";
688 pinctrl-0 = <&pinctrl_uart1>;
689 status = "okay";
690};
691
692&usbh1 {
693 vbus-supply = <&reg_usb_h1_vbus>;
694 status = "okay";
695};
696
697&usbotg {
698 vbus-supply = <&reg_usb_otg_vbus>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_usbotg>;
701 disable-over-current;
702 status = "okay";
703};
704
705&usdhc2 {
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_usdhc2>;
708 bus-width = <8>;
709 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
710 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
711 status = "okay";
712};
713
714&usdhc3 {
715 pinctrl-names = "default";
716 pinctrl-0 = <&pinctrl_usdhc3>;
717 bus-width = <8>;
718 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
719 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
720 status = "okay";
721};
722
723&usdhc4 {
724 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_usdhc4>;
726 bus-width = <8>;
727 non-removable;
728 no-1-8-v;
729 status = "okay";
730};
731
732&wdog1 {
733 status = "disabled";
734};
735
736&wdog2 {
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_wdog>;
739 fsl,ext-reset-output;
740 status = "okay";
741};