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git01.mediatek.com / filogic / uboot / d42247d630547bebc216c9e5807d784ba94e264e / . / arch / arm / dts / imx8mn-beacon-som.dtsi
blob: 52a50d97e0508f6d79079df6f662d7a17926a856 [file] [log] [blame]
Adam Fordd42247d2020-12-11 06:01:46 -0600[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6/ {
7 usdhc1_pwrseq: usdhc1_pwrseq {
8 compatible = "mmc-pwrseq-simple";
9 pinctrl-names = "default";
10 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
11 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
12 clocks = <&osc_32k>;
13 clock-names = "ext_clock";
14 post-power-on-delay-ms = <80>;
15 };
16
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x0 0x40000000 0 0x80000000>;
20 };
21};
22
23&A53_0 {
24 cpu-supply = <&buck2_reg>;
25};
26
27&A53_1 {
28 cpu-supply = <&buck2_reg>;
29};
30
31&A53_2 {
32 cpu-supply = <&buck2_reg>;
33};
34
35&A53_3 {
36 cpu-supply = <&buck2_reg>;
37};
38
39&fec1 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_fec1>;
42 phy-mode = "rgmii-id";
43 phy-handle = <&ethphy0>;
44 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
45 fsl,magic-packet;
46 status = "okay";
47
48 mdio {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ethphy0: ethernet-phy@0 {
53 compatible = "ethernet-phy-ieee802.3-c22";
54 reg = <0>;
55 };
56 };
57};
58
59&i2c1 {
60 clock-frequency = <400000>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_i2c1>;
63 status = "okay";
64
65 pmic@4b {
66 compatible = "rohm,bd71847";
67 reg = <0x4b>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pmic>;
70 interrupt-parent = <&gpio1>;
71 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
72 rohm,reset-snvs-powered;
73
74 regulators {
75 buck1_reg: BUCK1 {
76 regulator-name = "buck1";
77 regulator-min-microvolt = <700000>;
78 regulator-max-microvolt = <1300000>;
79 regulator-boot-on;
80 regulator-always-on;
81 regulator-ramp-delay = <1250>;
82 };
83
84 buck2_reg: BUCK2 {
85 regulator-name = "buck2";
86 regulator-min-microvolt = <700000>;
87 regulator-max-microvolt = <1300000>;
88 regulator-boot-on;
89 regulator-always-on;
90 regulator-ramp-delay = <1250>;
91 rohm,dvs-run-voltage = <1000000>;
92 rohm,dvs-idle-voltage = <900000>;
93 };
94
95 buck3_reg: BUCK3 {
96 // BUCK5 in datasheet
97 regulator-name = "buck3";
98 regulator-min-microvolt = <700000>;
99 regulator-max-microvolt = <1350000>;
100 regulator-boot-on;
101 regulator-always-on;
102 };
103
104 buck4_reg: BUCK4 {
105 // BUCK6 in datasheet
106 regulator-name = "buck4";
107 regulator-min-microvolt = <3000000>;
108 regulator-max-microvolt = <3300000>;
109 regulator-boot-on;
110 regulator-always-on;
111 };
112
113 buck5_reg: BUCK5 {
114 // BUCK7 in datasheet
115 regulator-name = "buck5";
116 regulator-min-microvolt = <1605000>;
117 regulator-max-microvolt = <1995000>;
118 regulator-boot-on;
119 regulator-always-on;
120 };
121
122 buck6_reg: BUCK6 {
123 // BUCK8 in datasheet
124 regulator-name = "buck6";
125 regulator-min-microvolt = <800000>;
126 regulator-max-microvolt = <1400000>;
127 regulator-boot-on;
128 regulator-always-on;
129 };
130
131 ldo1_reg: LDO1 {
132 regulator-name = "ldo1";
133 regulator-min-microvolt = <1600000>;
134 regulator-max-microvolt = <3300000>;
135 regulator-boot-on;
136 regulator-always-on;
137 };
138
139 ldo2_reg: LDO2 {
140 regulator-name = "ldo2";
141 regulator-min-microvolt = <800000>;
142 regulator-max-microvolt = <900000>;
143 regulator-boot-on;
144 regulator-always-on;
145 };
146
147 ldo3_reg: LDO3 {
148 regulator-name = "ldo3";
149 regulator-min-microvolt = <1800000>;
150 regulator-max-microvolt = <3300000>;
151 regulator-boot-on;
152 regulator-always-on;
153 };
154
155 ldo4_reg: LDO4 {
156 regulator-name = "ldo4";
157 regulator-min-microvolt = <900000>;
158 regulator-max-microvolt = <1800000>;
159 regulator-boot-on;
160 regulator-always-on;
161 };
162
163 ldo6_reg: LDO6 {
164 regulator-name = "ldo6";
165 regulator-min-microvolt = <900000>;
166 regulator-max-microvolt = <1800000>;
167 regulator-boot-on;
168 regulator-always-on;
169 };
170 };
171 };
172};
173
174&i2c3 {
175 clock-frequency = <400000>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_i2c3>;
178 status = "okay";
179
180 eeprom@50 {
181 compatible = "microchip,24c64", "atmel,24c64";
182 pagesize = <32>;
183 read-only; /* Manufacturing EEPROM programmed at factory */
184 reg = <0x50>;
185 };
186
187 rtc@51 {
188 compatible = "nxp,pcf85263";
189 reg = <0x51>;
190 };
191};
192
193&uart1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart1>;
196 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
197 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
198 uart-has-rtscts;
199 status = "okay";
200
201 bluetooth {
202 compatible = "brcm,bcm43438-bt";
203 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
204 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
205 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
206 clocks = <&osc_32k>;
207 max-speed = <4000000>;
208 clock-names = "extclk";
209 };
210};
211
212&usdhc1 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_usdhc1>;
217 bus-width = <4>;
218 non-removable;
219 cap-power-off-card;
220 pm-ignore-notify;
221 keep-power-in-suspend;
222 mmc-pwrseq = <&usdhc1_pwrseq>;
223 status = "okay";
224
225 brcmf: bcrmf@1 {
226 reg = <1>;
227 compatible = "brcm,bcm4329-fmac";
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_wlan>;
230 interrupt-parent = <&gpio2>;
231 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-names = "host-wake";
233 };
234};
235
236&usdhc3 {
237 pinctrl-names = "default", "state_100mhz", "state_200mhz";
238 pinctrl-0 = <&pinctrl_usdhc3>;
239 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
240 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
241 bus-width = <8>;
242 non-removable;
243 status = "okay";
244};
245
246&wdog1 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_wdog>;
249 fsl,ext-reset-output;
250 status = "okay";
251};
252
253&iomuxc {
254 pinctrl_fec1: fec1grp {
255 fsl,pins = <
256 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
257 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
258 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
259 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
260 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
261 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
262 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
263 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
264 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
265 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
266 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
267 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
268 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
269 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
270 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
271 >;
272 };
273
274 pinctrl_i2c1: i2c1grp {
275 fsl,pins = <
276 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
277 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
278 >;
279 };
280
281 pinctrl_i2c3: i2c3grp {
282 fsl,pins = <
283 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
284 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
285 >;
286 };
287
288 pinctrl_pmic: pmicirqgrp {
289 fsl,pins = <
290 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
291 >;
292 };
293
294 pinctrl_uart1: uart1grp {
295 fsl,pins = <
296 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
297 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
298 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
299 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
300 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
301 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
302 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
303 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
304 >;
305 };
306
307 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
308 fsl,pins = <
309 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
310 >;
311 };
312
313 pinctrl_usdhc1: usdhc1grp {
314 fsl,pins = <
315 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
316 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
317 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
318 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
319 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
320 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
321 >;
322 };
323
324 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
325 fsl,pins = <
326 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
327 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
328 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
329 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
330 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
331 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
332 >;
333 };
334
335 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
336 fsl,pins = <
337 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
338 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
339 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
340 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
341 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
342 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
343 >;
344 };
345
346 pinctrl_usdhc3: usdhc3grp {
347 fsl,pins = <
348 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
349 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
350 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
351 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
352 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
353 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
354 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
355 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
356 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
357 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
358 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
359 >;
360 };
361
362 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
363 fsl,pins = <
364 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
365 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
366 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
367 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
368 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
369 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
370 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
371 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
372 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
373 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
374 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
375 >;
376 };
377
378 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
379 fsl,pins = <
380 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
381 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
382 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
383 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
384 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
385 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
386 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
387 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
388 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
389 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
390 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
391 >;
392 };
393
394 pinctrl_wdog: wdoggrp {
395 fsl,pins = <
396 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
397 >;
398 };
399
400 pinctrl_wlan: wlangrp {
401 fsl,pins = <
402 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
403 >;
404 };
405};