wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * mcf5282.h -- Definitions for Motorola Coldfire 5282 |
| 3 | * |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /****************************************************************************/ |
| 24 | #ifndef m5282_h |
| 25 | #define m5282_h |
| 26 | /****************************************************************************/ |
| 27 | |
| 28 | /* |
| 29 | * Size of internal RAM |
| 30 | */ |
| 31 | |
| 32 | #define INT_RAM_SIZE 65536 |
| 33 | |
Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 34 | /* General Purpose I/O Module GPIO */ |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 35 | |
Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 36 | #define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000)) |
| 37 | #define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001)) |
| 38 | #define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002)) |
| 39 | #define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003)) |
| 40 | #define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004)) |
| 41 | #define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005)) |
| 42 | #define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006)) |
| 43 | #define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007)) |
| 44 | #define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008)) |
| 45 | #define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009)) |
| 46 | #define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A)) |
| 47 | #define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B)) |
| 48 | #define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C)) |
| 49 | #define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D)) |
| 50 | #define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E)) |
| 51 | #define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F)) |
| 52 | #define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010)) |
| 53 | #define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011)) |
| 54 | |
| 55 | #define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014)) |
| 56 | #define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015)) |
| 57 | #define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016)) |
| 58 | #define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017)) |
| 59 | #define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018)) |
| 60 | #define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019)) |
| 61 | #define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A)) |
| 62 | #define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B)) |
| 63 | #define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C)) |
| 64 | #define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D)) |
| 65 | #define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E)) |
| 66 | #define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F)) |
| 67 | #define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020)) |
| 68 | #define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021)) |
| 69 | #define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022)) |
| 70 | #define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023)) |
| 71 | #define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024)) |
| 72 | #define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025)) |
| 73 | |
| 74 | #define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028)) |
| 75 | #define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029)) |
| 76 | #define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A)) |
| 77 | #define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B)) |
| 78 | #define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C)) |
| 79 | #define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D)) |
| 80 | #define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E)) |
| 81 | #define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F)) |
| 82 | #define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030)) |
| 83 | #define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031)) |
| 84 | #define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032)) |
| 85 | #define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033)) |
| 86 | #define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034)) |
| 87 | #define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035)) |
| 88 | #define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036)) |
| 89 | #define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037)) |
| 90 | #define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038)) |
| 91 | #define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039)) |
| 92 | |
| 93 | #define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028)) |
| 94 | #define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029)) |
| 95 | #define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A)) |
| 96 | #define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) |
| 97 | #define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) |
| 98 | #define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) |
| 99 | #define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) |
| 100 | #define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) |
| 101 | #define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) |
| 102 | #define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) |
| 103 | #define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) |
| 104 | #define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) |
| 105 | #define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) |
| 106 | #define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) |
| 107 | #define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) |
| 108 | #define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) |
| 109 | #define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) |
| 110 | #define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) |
| 111 | |
| 112 | #define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) |
| 113 | #define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) |
| 114 | #define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) |
| 115 | #define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) |
| 116 | #define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) |
| 117 | #define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) |
| 118 | #define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) |
| 119 | #define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) |
| 120 | #define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) |
| 121 | #define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) |
| 122 | #define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) |
| 123 | #define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) |
| 124 | #define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) |
| 125 | #define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) |
| 126 | #define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) |
| 127 | #define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) |
| 128 | #define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) |
| 129 | #define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) |
| 130 | |
| 131 | #define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) |
| 132 | #define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) |
| 133 | #define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) |
| 134 | #define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) |
| 135 | #define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) |
| 136 | #define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) |
| 137 | #define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) |
| 138 | #define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) |
| 139 | #define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) |
| 140 | #define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) |
| 141 | #define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) |
| 142 | |
| 143 | /* Bit level definitions and macros */ |
| 144 | #define MCFGPIO_PORT7 (0x80) |
| 145 | #define MCFGPIO_PORT6 (0x40) |
| 146 | #define MCFGPIO_PORT5 (0x20) |
| 147 | #define MCFGPIO_PORT4 (0x10) |
| 148 | #define MCFGPIO_PORT3 (0x08) |
| 149 | #define MCFGPIO_PORT2 (0x04) |
| 150 | #define MCFGPIO_PORT1 (0x02) |
| 151 | #define MCFGPIO_PORT0 (0x01) |
| 152 | #define MCFGPIO_PORT(x) (0x01<<x) |
| 153 | |
| 154 | #define MCFGPIO_DDR7 (0x80) |
| 155 | #define MCFGPIO_DDR6 (0x40) |
| 156 | #define MCFGPIO_DDR5 (0x20) |
| 157 | #define MCFGPIO_DDR4 (0x10) |
| 158 | #define MCFGPIO_DDR3 (0x08) |
| 159 | #define MCFGPIO_DDR2 (0x04) |
| 160 | #define MCFGPIO_DDR1 (0x02) |
| 161 | #define MCFGPIO_DDR0 (0x01) |
| 162 | #define MCFGPIO_DDR(x) (0x01<<x) |
| 163 | |
| 164 | #define MCFGPIO_Px7 (0x80) |
| 165 | #define MCFGPIO_Px6 (0x40) |
| 166 | #define MCFGPIO_Px5 (0x20) |
| 167 | #define MCFGPIO_Px4 (0x10) |
| 168 | #define MCFGPIO_Px3 (0x08) |
| 169 | #define MCFGPIO_Px2 (0x04) |
| 170 | #define MCFGPIO_Px1 (0x02) |
| 171 | #define MCFGPIO_Px0 (0x01) |
| 172 | #define MCFGPIO_Px(x) (0x01<<x) |
| 173 | |
| 174 | |
| 175 | #define MCFGPIO_PBCDPAR_PBPA (0x80) |
| 176 | #define MCFGPIO_PBCDPAR_PCDPA (0x40) |
| 177 | |
| 178 | #define MCFGPIO_PEPAR_PEPA7 (0x4000) |
| 179 | #define MCFGPIO_PEPAR_PEPA6 (0x1000) |
| 180 | #define MCFGPIO_PEPAR_PEPA5 (0x0400) |
| 181 | #define MCFGPIO_PEPAR_PEPA4 (0x0100) |
| 182 | #define MCFGPIO_PEPAR_PEPA3 (0x0040) |
| 183 | #define MCFGPIO_PEPAR_PEPA2 (0x0010) |
| 184 | #define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2) |
| 185 | #define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3)) |
| 186 | |
| 187 | #define MCFGPIO_PFPAR_PFPA7 (0x80) |
| 188 | #define MCFGPIO_PFPAR_PFPA6 (0x40) |
| 189 | #define MCFGPIO_PFPAR_PFPA5 (0x20) |
| 190 | |
| 191 | #define MCFGPIO_PJPAR_PJPA7 (0x80) |
| 192 | #define MCFGPIO_PJPAR_PJPA6 (0x40) |
| 193 | #define MCFGPIO_PJPAR_PJPA5 (0x20) |
| 194 | #define MCFGPIO_PJPAR_PJPA4 (0x10) |
| 195 | #define MCFGPIO_PJPAR_PJPA3 (0x08) |
| 196 | #define MCFGPIO_PJPAR_PJPA2 (0x04) |
| 197 | #define MCFGPIO_PJPAR_PJPA1 (0x02) |
| 198 | #define MCFGPIO_PJPAR_PJPA0 (0x01) |
| 199 | #define MCFGPIO_PJPAR_PJPA(x) (0x01<<x) |
| 200 | |
| 201 | #define MCFGPIO_PSDPAR_PSDPA (0x80) |
| 202 | |
| 203 | #define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10) |
| 204 | #define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8) |
| 205 | #define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6) |
| 206 | #define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4) |
| 207 | #define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2) |
| 208 | #define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3)) |
| 209 | |
| 210 | #define MCFGPIO_PEHLPAR_PEHPA (0x80) |
| 211 | #define MCFGPIO_PEHLPAR_PELPA (0x40) |
| 212 | |
| 213 | #define MCFGPIO_PQSPAR_PQSPA6 (0x40) |
| 214 | #define MCFGPIO_PQSPAR_PQSPA5 (0x20) |
| 215 | #define MCFGPIO_PQSPAR_PQSPA4 (0x10) |
| 216 | #define MCFGPIO_PQSPAR_PQSPA3 (0x08) |
| 217 | #define MCFGPIO_PQSPAR_PQSPA2 (0x04) |
| 218 | #define MCFGPIO_PQSPAR_PQSPA1 (0x02) |
| 219 | #define MCFGPIO_PQSPAR_PQSPA0 (0x01) |
| 220 | #define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x) |
| 221 | |
| 222 | #define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6) |
| 223 | #define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4) |
| 224 | #define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2) |
| 225 | #define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3)) |
| 226 | |
| 227 | #define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6) |
| 228 | #define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4) |
| 229 | #define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2) |
| 230 | #define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3)) |
| 231 | |
| 232 | #define MCFGPIO_PUAPAR_PUAPA3 (0x08) |
| 233 | #define MCFGPIO_PUAPAR_PUAPA2 (0x04) |
| 234 | #define MCFGPIO_PUAPAR_PUAPA1 (0x02) |
| 235 | #define MCFGPIO_PUAPAR_PUAPA0 (0x01) |
| 236 | |
| 237 | /* System Conrol Module SCM */ |
| 238 | |
| 239 | #define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008)) |
| 240 | #define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010)) |
| 241 | #define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011)) |
| 242 | #define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012)) |
| 243 | #define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013)) |
| 244 | |
| 245 | #define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C)) |
| 246 | #define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020)) |
| 247 | #define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024)) |
| 248 | #define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025)) |
| 249 | #define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026)) |
| 250 | #define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027)) |
| 251 | #define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028)) |
| 252 | #define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A)) |
| 253 | #define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B)) |
| 254 | #define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C)) |
| 255 | #define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E)) |
| 256 | #define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030)) |
| 257 | #define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031)) |
| 258 | |
| 259 | |
| 260 | #define MCFSCM_CRSR_EXT (0x80) |
| 261 | #define MCFSCM_CRSR_CWDR (0x20) |
| 262 | #define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000) |
| 263 | #define MCFSCM_RAMBAR_BDE (0x00000200) |
| 264 | |
| 265 | /* Reset Controller Module RCM */ |
| 266 | |
| 267 | #define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000)) |
| 268 | #define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001)) |
| 269 | |
| 270 | #define MCFRESET_RCR_SOFTRST (0x80) |
| 271 | #define MCFRESET_RCR_FRCRSTOUT (0x40) |
| 272 | #define MCFRESET_RCR_LVDF (0x10) |
| 273 | #define MCFRESET_RCR_LVDIE (0x08) |
| 274 | #define MCFRESET_RCR_LVDRE (0x04) |
| 275 | #define MCFRESET_RCR_LVDE (0x01) |
| 276 | |
| 277 | #define MCFRESET_RSR_LVD (0x40) |
| 278 | #define MCFRESET_RSR_SOFT (0x20) |
| 279 | #define MCFRESET_RSR_WDR (0x10) |
| 280 | #define MCFRESET_RSR_POR (0x08) |
| 281 | #define MCFRESET_RSR_EXT (0x04) |
| 282 | #define MCFRESET_RSR_LOC (0x02) |
| 283 | #define MCFRESET_RSR_LOL (0x01) |
| 284 | #define MCFRESET_RSR_ALL (0x7F) |
| 285 | #define MCFRESET_RCR_SOFTRST (0x80) |
| 286 | #define MCFRESET_RCR_FRCRSTOUT (0x40) |
| 287 | |
| 288 | /* Chip Configuration Module CCM */ |
| 289 | |
| 290 | #define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004)) |
| 291 | #define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008)) |
| 292 | #define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A)) |
| 293 | |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 294 | |
Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 295 | /* Bit level definitions and macros */ |
| 296 | #define MCFCCM_CCR_LOAD (0x8000) |
| 297 | #define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8) |
| 298 | #define MCFCCM_CCR_SZEN (0x0040) |
| 299 | #define MCFCCM_CCR_PSTEN (0x0020) |
| 300 | #define MCFCCM_CCR_BME (0x0008) |
| 301 | #define MCFCCM_CCR_BMT(x) (((x)&0x0007)) |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 302 | |
Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 303 | #define MCFCCM_CIR_PIN_MASK (0xFF00) |
| 304 | #define MCFCCM_CIR_PRN_MASK (0x00FF) |
| 305 | |
| 306 | /* Clock Module */ |
| 307 | |
| 308 | #define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000)) |
| 309 | #define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002)) |
| 310 | |
| 311 | #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) |
| 312 | #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) |
| 313 | #define MCFCLOCK_SYNSR_LOCK 0x08 |
| 314 | |
| 315 | #define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040)) |
| 316 | #define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048)) |
| 317 | #define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c)) |
| 318 | #define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050)) |
| 319 | #define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054)) |
| 320 | |
| 321 | #define MCFSDRAMC_DCR_NAM (0x2000) |
| 322 | #define MCFSDRAMC_DCR_COC (0x1000) |
| 323 | #define MCFSDRAMC_DCR_IS (0x0800) |
| 324 | #define MCFSDRAMC_DCR_RTIM_3 (0x0000) |
| 325 | #define MCFSDRAMC_DCR_RTIM_6 (0x0200) |
| 326 | #define MCFSDRAMC_DCR_RTIM_9 (0x0400) |
| 327 | #define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF) |
| 328 | |
| 329 | #define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000) |
| 330 | #define MCFSDRAMC_DACR_RE (0x00008000) |
| 331 | #define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12) |
| 332 | #define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8) |
| 333 | #define MCFSDRAMC_DACR_PS_32 (0x00000000) |
| 334 | #define MCFSDRAMC_DACR_PS_16 (0x00000020) |
| 335 | #define MCFSDRAMC_DACR_PS_8 (0x00000010) |
| 336 | #define MCFSDRAMC_DACR_IP (0x00000008) |
| 337 | #define MCFSDRAMC_DACR_IMRS (0x00000040) |
| 338 | |
| 339 | #define MCFSDRAMC_DMR_BAM_16M (0x00FC0000) |
| 340 | #define MCFSDRAMC_DMR_WP (0x00000100) |
| 341 | #define MCFSDRAMC_DMR_CI (0x00000040) |
| 342 | #define MCFSDRAMC_DMR_AM (0x00000020) |
| 343 | #define MCFSDRAMC_DMR_SC (0x00000010) |
| 344 | #define MCFSDRAMC_DMR_SD (0x00000008) |
| 345 | #define MCFSDRAMC_DMR_UC (0x00000004) |
| 346 | #define MCFSDRAMC_DMR_UD (0x00000002) |
| 347 | #define MCFSDRAMC_DMR_V (0x00000001) |
| 348 | |
| 349 | #define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000)) |
| 350 | #define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002)) |
| 351 | #define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004)) |
| 352 | #define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006)) |
| 353 | |
| 354 | /* Chip SELECT Module CSM */ |
| 355 | #define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080)) |
| 356 | #define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084)) |
| 357 | #define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a)) |
| 358 | #define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C)) |
| 359 | #define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090)) |
| 360 | #define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096)) |
| 361 | #define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098)) |
| 362 | #define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C)) |
| 363 | #define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2)) |
| 364 | #define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4)) |
| 365 | #define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8)) |
| 366 | #define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE)) |
| 367 | |
| 368 | #define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000) |
| 369 | #define MCFCSM_CSMR_WP (1<<8) |
| 370 | #define MCFCSM_CSMR_V (0x01) |
| 371 | #define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10) |
| 372 | #define MCFCSM_CSCR_AA (0x0100) |
| 373 | #define MCFCSM_CSCR_PS_32 (0x0000) |
| 374 | #define MCFCSM_CSCR_PS_8 (0x0040) |
| 375 | #define MCFCSM_CSCR_PS_16 (0x0080) |
| 376 | |
| 377 | /********************************************************************* |
| 378 | * |
| 379 | * General Purpose Timer (GPT) Module |
| 380 | * |
| 381 | *********************************************************************/ |
| 382 | |
| 383 | #define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000)) |
| 384 | #define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001)) |
| 385 | #define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002)) |
| 386 | #define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003)) |
| 387 | #define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004)) |
| 388 | #define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006)) |
| 389 | #define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008)) |
| 390 | #define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009)) |
| 391 | #define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B)) |
| 392 | #define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C)) |
| 393 | #define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D)) |
| 394 | #define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E)) |
| 395 | #define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F)) |
| 396 | #define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010)) |
| 397 | #define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012)) |
| 398 | #define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014)) |
| 399 | #define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016)) |
| 400 | #define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018)) |
| 401 | #define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019)) |
| 402 | #define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A)) |
| 403 | #define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D)) |
| 404 | #define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E)) |
| 405 | |
| 406 | |
| 407 | #define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000)) |
| 408 | #define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001)) |
| 409 | #define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002)) |
| 410 | #define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003)) |
| 411 | #define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004)) |
| 412 | #define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006)) |
| 413 | #define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008)) |
| 414 | #define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009)) |
| 415 | #define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B)) |
| 416 | #define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C)) |
| 417 | #define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D)) |
| 418 | #define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E)) |
| 419 | #define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F)) |
| 420 | #define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010)) |
| 421 | #define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012)) |
| 422 | #define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014)) |
| 423 | #define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016)) |
| 424 | #define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018)) |
| 425 | #define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019)) |
| 426 | #define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A)) |
| 427 | #define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D)) |
| 428 | #define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E)) |
| 429 | |
| 430 | /* Bit level definitions and macros */ |
| 431 | #define MCFGPT_GPTIOS_IOS3 (0x08) |
| 432 | #define MCFGPT_GPTIOS_IOS2 (0x04) |
| 433 | #define MCFGPT_GPTIOS_IOS1 (0x02) |
| 434 | #define MCFGPT_GPTIOS_IOS0 (0x01) |
| 435 | |
| 436 | #define MCFGPT_GPTCFORC_FOC3 (0x08) |
| 437 | #define MCFGPT_GPTCFORC_FOC2 (0x04) |
| 438 | #define MCFGPT_GPTCFORC_FOC1 (0x02) |
| 439 | #define MCFGPT_GPTCFORC_FOC0 (0x01) |
| 440 | |
| 441 | #define MCFGPT_GPTOC3M_OC3M3 (0x08) |
| 442 | #define MCFGPT_GPTOC3M_OC3M2 (0x04) |
| 443 | #define MCFGPT_GPTOC3M_OC3M1 (0x02) |
| 444 | #define MCFGPT_GPTOC3M_OC3M0 (0x01) |
| 445 | |
| 446 | #define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04)) |
| 447 | |
| 448 | #define MCFGPT_GPTSCR1_GPTEN (0x80) |
| 449 | #define MCFGPT_GPTSCR1_TFFCA (0x10) |
| 450 | |
| 451 | #define MCFGPT_GPTTOV3 (0x08) |
| 452 | #define MCFGPT_GPTTOV2 (0x04) |
| 453 | #define MCFGPT_GPTTOV1 (0x02) |
| 454 | #define MCFGPT_GPTTOV0 (0x01) |
| 455 | |
| 456 | #define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6) |
| 457 | #define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4) |
| 458 | #define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2) |
| 459 | #define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03)) |
| 460 | |
| 461 | #define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6) |
| 462 | #define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4) |
| 463 | #define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2) |
| 464 | #define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03)) |
| 465 | |
| 466 | #define MCFGPT_GPTIE_C3I (0x08) |
| 467 | #define MCFGPT_GPTIE_C2I (0x04) |
| 468 | #define MCFGPT_GPTIE_C1I (0x02) |
| 469 | #define MCFGPT_GPTIE_C0I (0x01) |
| 470 | |
| 471 | #define MCFGPT_GPTSCR2_TOI (0x80) |
| 472 | #define MCFGPT_GPTSCR2_PUPT (0x20) |
| 473 | #define MCFGPT_GPTSCR2_RDPT (0x10) |
| 474 | #define MCFGPT_GPTSCR2_TCRE (0x08) |
| 475 | #define MCFGPT_GPTSCR2_PR(x) (((x)&0x07)) |
| 476 | |
| 477 | #define MCFGPT_GPTFLG1_C3F (0x08) |
| 478 | #define MCFGPT_GPTFLG1_C2F (0x04) |
| 479 | #define MCFGPT_GPTFLG1_C1F (0x02) |
| 480 | #define MCFGPT_GPTFLG1_C0F (0x01) |
| 481 | |
| 482 | #define MCFGPT_GPTFLG2_TOF (0x80) |
| 483 | #define MCFGPT_GPTFLG2_C3F (0x08) |
| 484 | #define MCFGPT_GPTFLG2_C2F (0x04) |
| 485 | #define MCFGPT_GPTFLG2_C1F (0x02) |
| 486 | #define MCFGPT_GPTFLG2_C0F (0x01) |
| 487 | |
| 488 | #define MCFGPT_GPTPACTL_PAE (0x40) |
| 489 | #define MCFGPT_GPTPACTL_PAMOD (0x20) |
| 490 | #define MCFGPT_GPTPACTL_PEDGE (0x10) |
| 491 | #define MCFGPT_GPTPACTL_CLK_PACLK (0x04) |
| 492 | #define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08) |
| 493 | #define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C) |
| 494 | #define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) |
| 495 | #define MCFGPT_GPTPACTL_PAOVI (0x02) |
| 496 | #define MCFGPT_GPTPACTL_PAI (0x01) |
| 497 | |
| 498 | #define MCFGPT_GPTPAFLG_PAOVF (0x02) |
| 499 | #define MCFGPT_GPTPAFLG_PAIF (0x01) |
| 500 | |
| 501 | #define MCFGPT_GPTPORT_PORTT3 (0x08) |
| 502 | #define MCFGPT_GPTPORT_PORTT2 (0x04) |
| 503 | #define MCFGPT_GPTPORT_PORTT1 (0x02) |
| 504 | #define MCFGPT_GPTPORT_PORTT0 (0x01) |
| 505 | |
| 506 | #define MCFGPT_GPTDDR_DDRT3 (0x08) |
| 507 | #define MCFGPT_GPTDDR_DDRT2 (0x04) |
| 508 | #define MCFGPT_GPTDDR_DDRT1 (0x02) |
| 509 | #define MCFGPT_GPTDDR_DDRT0 (0x01) |
| 510 | |
| 511 | /* Coldfire Flash Module CFM */ |
| 512 | |
| 513 | #define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000)) |
| 514 | #define MCFCFM_MCR_LOCK (0x0400) |
| 515 | #define MCFCFM_MCR_PVIE (0x0200) |
| 516 | #define MCFCFM_MCR_AEIE (0x0100) |
| 517 | #define MCFCFM_MCR_CBEIE (0x0080) |
| 518 | #define MCFCFM_MCR_CCIE (0x0040) |
| 519 | #define MCFCFM_MCR_KEYACC (0x0020) |
| 520 | |
| 521 | #define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002)) |
| 522 | |
| 523 | #define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008)) |
| 524 | #define MCFCFM_SEC_KEYEN (0x80000000) |
| 525 | #define MCFCFM_SEC_SECSTAT (0x40000000) |
| 526 | |
| 527 | #define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010)) |
| 528 | #define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014)) |
| 529 | #define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018)) |
| 530 | #define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020)) |
| 531 | #define MCFCFM_USTAT_CBEIF 0x80 |
| 532 | #define MCFCFM_USTAT_CCIF 0x40 |
| 533 | #define MCFCFM_USTAT_PVIOL 0x20 |
| 534 | #define MCFCFM_USTAT_ACCERR 0x10 |
| 535 | #define MCFCFM_USTAT_BLANK 0x04 |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 536 | |
Heiko Schocher | ac1956e | 2006-04-20 08:42:42 +0200 | [diff] [blame] | 537 | #define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024)) |
| 538 | #define MCFCFM_CMD_ERSVER 0x05 |
| 539 | #define MCFCFM_CMD_PGERSVER 0x06 |
| 540 | #define MCFCFM_CMD_PGM 0x20 |
| 541 | #define MCFCFM_CMD_PGERS 0x40 |
| 542 | #define MCFCFM_CMD_MASERS 0x41 |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 543 | |
| 544 | /****************************************************************************/ |
| 545 | #endif /* m5282_h */ |