blob: ca030c8c41bf448a2059a517c8a6d42c0c3d5d05 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutb06dad22018-02-24 23:34:00 +01002/*
3 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
Marek Vasutb06dad22018-02-24 23:34:00 +01004 */
5
6#include "socfpga_cyclone5.dtsi"
Simon Goldschmidt64a12bf2019-03-01 20:12:29 +01007#include "socfpga-common-u-boot.dtsi"
Marek Vasutb06dad22018-02-24 23:34:00 +01008
9/ {
10 model = "Devboards.de DBM-SoC1";
11 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
12
13 chosen {
14 bootargs = "console=ttyS0,115200";
Simon Goldschmidt3854a1a2018-08-13 21:34:33 +020015 stdout-path = "serial0:115200n8";
Marek Vasutb06dad22018-02-24 23:34:00 +010016 };
17
18 aliases {
19 ethernet0 = &gmac1;
20 udc0 = &usb1;
21 };
22
23 memory {
24 name = "memory";
25 device_type = "memory";
26 reg = <0x0 0x40000000>; /* 1GB */
27 };
Marek Vasutb06dad22018-02-24 23:34:00 +010028};
29
30&gmac1 {
31 status = "okay";
32 phy-mode = "rgmii";
33};
34
35&gpio0 {
36 status = "okay";
37};
38
39&gpio1 {
40 status = "okay";
41};
42
43&gpio2 {
44 status = "okay";
45};
46
Simon Goldschmidt15616b52018-11-02 11:54:52 +010047&porta {
48 bank-name = "porta";
49};
50
51&portb {
52 bank-name = "portb";
53};
54
55&portc {
56 bank-name = "portc";
57};
58
Marek Vasutb06dad22018-02-24 23:34:00 +010059&mmc0 {
60 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -070061 bootph-all;
Marek Vasutb06dad22018-02-24 23:34:00 +010062};
63
64&usb1 {
65 disable-over-current;
66 status = "okay";
67};
Simon Goldschmidt3854a1a2018-08-13 21:34:33 +020068
69&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070070 bootph-all;
Simon Goldschmidt3854a1a2018-08-13 21:34:33 +020071};
Simon Goldschmidt15616b52018-11-02 11:54:52 +010072
73&watchdog0 {
74 status = "disabled";
75};