| Eugeniy Paltsev | 062da42 | 2019-10-08 19:29:30 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * HSDK SoC Reset Controller driver |
| 4 | * |
| 5 | * Copyright (C) 2019 Synopsys, Inc. All rights reserved. |
| 6 | * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
| 7 | */ |
| 8 | |
| 9 | #include <asm/io.h> |
| 10 | #include <common.h> |
| 11 | #include <dm.h> |
| 12 | #include <linux/iopoll.h> |
| 13 | #include <reset-uclass.h> |
| 14 | |
| 15 | struct hsdk_rst { |
| 16 | void __iomem *regs_ctl; |
| 17 | void __iomem *regs_rst; |
| 18 | }; |
| 19 | |
| 20 | static const u32 rst_map[] = { |
| 21 | BIT(16), /* APB_RST */ |
| 22 | BIT(17), /* AXI_RST */ |
| 23 | BIT(18), /* ETH_RST */ |
| 24 | BIT(19), /* USB_RST */ |
| 25 | BIT(20), /* SDIO_RST */ |
| 26 | BIT(21), /* HDMI_RST */ |
| 27 | BIT(22), /* GFX_RST */ |
| 28 | BIT(25), /* DMAC_RST */ |
| 29 | BIT(31), /* EBI_RST */ |
| 30 | }; |
| 31 | |
| 32 | #define HSDK_MAX_RESETS ARRAY_SIZE(rst_map) |
| 33 | |
| 34 | #define CGU_SYS_RST_CTRL 0x0 |
| 35 | #define CGU_IP_SW_RESET 0x0 |
| 36 | #define CGU_IP_SW_RESET_DELAY_SHIFT 16 |
| 37 | #define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT) |
| 38 | #define CGU_IP_SW_RESET_DELAY 0 |
| 39 | #define CGU_IP_SW_RESET_RESET BIT(0) |
| 40 | #define SW_RESET_TIMEOUT 10000 |
| 41 | |
| 42 | static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id) |
| 43 | { |
| 44 | writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL); |
| 45 | } |
| 46 | |
| 47 | static int hsdk_reset_do(struct hsdk_rst *rst) |
| 48 | { |
| 49 | u32 reg; |
| 50 | |
| 51 | reg = readl(rst->regs_rst + CGU_IP_SW_RESET); |
| 52 | reg &= ~CGU_IP_SW_RESET_DELAY_MASK; |
| 53 | reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT; |
| 54 | reg |= CGU_IP_SW_RESET_RESET; |
| 55 | writel(reg, rst->regs_rst + CGU_IP_SW_RESET); |
| 56 | |
| 57 | /* wait till reset bit is back to 0 */ |
| 58 | return readl_poll_timeout(rst->regs_rst + CGU_IP_SW_RESET, reg, |
| 59 | !(reg & CGU_IP_SW_RESET_RESET), SW_RESET_TIMEOUT); |
| 60 | } |
| 61 | |
| 62 | static int hsdk_reset_reset(struct reset_ctl *rst_ctl) |
| 63 | { |
| 64 | struct udevice *dev = rst_ctl->dev; |
| 65 | struct hsdk_rst *rst = dev_get_priv(dev); |
| 66 | |
| 67 | if (rst_ctl->id >= HSDK_MAX_RESETS) |
| 68 | return -EINVAL; |
| 69 | |
| 70 | debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, rst_ctl, |
| 71 | rst_ctl->dev, rst_ctl->id); |
| 72 | |
| 73 | hsdk_reset_config(rst, rst_ctl->id); |
| 74 | return hsdk_reset_do(rst); |
| 75 | } |
| 76 | |
| 77 | static int hsdk_reset_noop(struct reset_ctl *rst_ctl) |
| 78 | { |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | static const struct reset_ops hsdk_reset_ops = { |
| 83 | .request = hsdk_reset_noop, |
| 84 | .free = hsdk_reset_noop, |
| 85 | .rst_assert = hsdk_reset_noop, |
| 86 | .rst_deassert = hsdk_reset_reset, |
| 87 | }; |
| 88 | |
| 89 | static const struct udevice_id hsdk_reset_dt_match[] = { |
| 90 | { .compatible = "snps,hsdk-reset" }, |
| 91 | { }, |
| 92 | }; |
| 93 | |
| 94 | static int hsdk_reset_probe(struct udevice *dev) |
| 95 | { |
| 96 | struct hsdk_rst *rst = dev_get_priv(dev); |
| 97 | |
| 98 | rst->regs_ctl = dev_remap_addr_index(dev, 0); |
| 99 | if (!rst->regs_ctl) |
| 100 | return -EINVAL; |
| 101 | |
| 102 | rst->regs_rst = dev_remap_addr_index(dev, 1); |
| 103 | if (!rst->regs_rst) |
| 104 | return -EINVAL; |
| 105 | |
| 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | U_BOOT_DRIVER(hsdk_reset) = { |
| 110 | .name = "hsdk-reset", |
| 111 | .id = UCLASS_RESET, |
| 112 | .of_match = hsdk_reset_dt_match, |
| 113 | .ops = &hsdk_reset_ops, |
| 114 | .probe = hsdk_reset_probe, |
| 115 | .priv_auto_alloc_size = sizeof(struct hsdk_rst), |
| 116 | }; |