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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Thomas Chou221d2ac2015-10-22 22:28:53 +08002/*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
7 * Scott McNutt <smcnutt@psyent.com>
Thomas Chou221d2ac2015-10-22 22:28:53 +08008 */
9
10#include <common.h>
11#include <dm.h>
12#include <errno.h>
13#include <timer.h>
14#include <asm/io.h>
15
Thomas Chou90b1d792015-10-31 20:54:16 +080016/* control register */
17#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
18#define ALTERA_TIMER_START BIT(2) /* Start timer */
19#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
20
Thomas Chou221d2ac2015-10-22 22:28:53 +080021struct altera_timer_regs {
22 u32 status; /* Timer status reg */
23 u32 control; /* Timer control reg */
24 u32 periodl; /* Timeout period low */
25 u32 periodh; /* Timeout period high */
26 u32 snapl; /* Snapshot low */
27 u32 snaph; /* Snapshot high */
28};
29
30struct altera_timer_platdata {
31 struct altera_timer_regs *regs;
Thomas Chou221d2ac2015-10-22 22:28:53 +080032};
33
Bin Mengab841b62015-11-24 13:31:17 -070034static int altera_timer_get_count(struct udevice *dev, u64 *count)
Thomas Chou221d2ac2015-10-22 22:28:53 +080035{
36 struct altera_timer_platdata *plat = dev->platdata;
37 struct altera_timer_regs *const regs = plat->regs;
38 u32 val;
39
40 /* Trigger update */
41 writel(0x0, &regs->snapl);
42
43 /* Read timer value */
44 val = readl(&regs->snapl) & 0xffff;
45 val |= (readl(&regs->snaph) & 0xffff) << 16;
Bin Mengab841b62015-11-24 13:31:17 -070046 *count = timer_conv_64(~val);
Thomas Chou221d2ac2015-10-22 22:28:53 +080047
48 return 0;
49}
50
51static int altera_timer_probe(struct udevice *dev)
52{
Thomas Chou221d2ac2015-10-22 22:28:53 +080053 struct altera_timer_platdata *plat = dev->platdata;
54 struct altera_timer_regs *const regs = plat->regs;
55
Thomas Chou221d2ac2015-10-22 22:28:53 +080056 writel(0, &regs->status);
57 writel(0, &regs->control);
58 writel(ALTERA_TIMER_STOP, &regs->control);
59
60 writel(0xffff, &regs->periodl);
61 writel(0xffff, &regs->periodh);
62 writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);
63
64 return 0;
65}
66
67static int altera_timer_ofdata_to_platdata(struct udevice *dev)
68{
69 struct altera_timer_platdata *plat = dev_get_platdata(dev);
70
Simon Glassba1dea42017-05-17 17:18:05 -060071 plat->regs = map_physmem(devfdt_get_addr(dev),
Thomas Choud82a4d32015-11-14 11:15:31 +080072 sizeof(struct altera_timer_regs),
73 MAP_NOCACHE);
Thomas Chou221d2ac2015-10-22 22:28:53 +080074
75 return 0;
76}
77
78static const struct timer_ops altera_timer_ops = {
79 .get_count = altera_timer_get_count,
80};
81
82static const struct udevice_id altera_timer_ids[] = {
Thomas Chou90b1d792015-10-31 20:54:16 +080083 { .compatible = "altr,timer-1.0" },
84 {}
Thomas Chou221d2ac2015-10-22 22:28:53 +080085};
86
87U_BOOT_DRIVER(altera_timer) = {
88 .name = "altera_timer",
89 .id = UCLASS_TIMER,
90 .of_match = altera_timer_ids,
91 .ofdata_to_platdata = altera_timer_ofdata_to_platdata,
92 .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
93 .probe = altera_timer_probe,
94 .ops = &altera_timer_ops,
Thomas Chou221d2ac2015-10-22 22:28:53 +080095};