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git01.mediatek.com / filogic / uboot / d38112ce12e2a796311cfb0b91e905fcf582a498 / . / configs / P1020RDB-PC_defconfig
blob: 57d5958125a7fa068755b81144a2ef9deb857525 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0xEFF40000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]3CONFIG_SYS_MALLOC_LEN=0x100000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]4CONFIG_ENV_SIZE=0x2000
5CONFIG_ENV_SECT_SIZE=0x20000
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]6CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]7CONFIG_ENV_ADDR=0xEFF20000
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]8CONFIG_MPC85xx=y
Simon Glass9fdc0de2017-05-17 03:25:15 -0600[diff] [blame]9# CONFIG_CMD_ERRATA is not set
York Sun443108bf2016-11-17 13:52:44 -0800[diff] [blame]10CONFIG_TARGET_P1020RDB_PC=y
Hou Zhiqiang224999f2019-08-20 09:35:28 +0000[diff] [blame]11CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
Tom Rinia7fa9762022-06-15 12:03:45 -0400[diff] [blame]12CONFIG_ENABLE_36BIT_PHYS=y
Tom Rini667dd4f2022-06-10 22:59:37 -0400[diff] [blame]13CONFIG_SYS_MPC85XX_NO_RESETVEC=y
Tom Rini7485ebf62022-06-20 08:07:45 -0400[diff] [blame]14CONFIG_PCIE1=y
15CONFIG_PCIE2=y
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]16CONFIG_MP=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]17CONFIG_FIT=y
18CONFIG_FIT_VERBOSE=y
19CONFIG_OF_BOARD_SETUP=y
20CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini5989fd42022-06-20 08:07:42 -0400[diff] [blame]21CONFIG_FSL_FIXED_MMC_LOCATION=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]22CONFIG_BOOTDELAY=10
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]23CONFIG_USE_BOOTCOMMAND=y
24CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]25CONFIG_BOARD_EARLY_INIT_F=y
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]26CONFIG_BOARD_EARLY_INIT_R=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]27# CONFIG_MISC_INIT_R is not set
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]28CONFIG_HUSH_PARSER=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]29# CONFIG_AUTO_COMPLETE is not set
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]30CONFIG_SYS_PBSIZE=276
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]31CONFIG_CMD_IMLS=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]32CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
33CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]34CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]35CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]36CONFIG_CMD_USB=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]37CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]38CONFIG_CMD_PING=y
Simon Glass027608e2017-05-17 03:25:25 -0600[diff] [blame]39# CONFIG_CMD_HASH is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]40CONFIG_CMD_EXT2=y
41CONFIG_CMD_FAT=y
Hou Zhiqiang224999f2019-08-20 09:35:28 +0000[diff] [blame]42CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]43CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]44CONFIG_ENV_IS_IN_FLASH=y
Tom Rini5fb860c2022-02-25 11:19:48 -0500[diff] [blame]45CONFIG_USE_BOOTFILE=y
46CONFIG_BOOTFILE="uImage"
Tom Rinife586752022-03-11 09:12:07 -0500[diff] [blame]47CONFIG_USE_ETHPRIME=y
48CONFIG_ETHPRIME="eTSEC1"
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]49CONFIG_DM=y
Tom Rini3f004772022-06-10 22:59:28 -0400[diff] [blame]50CONFIG_LBA48=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]51CONFIG_DDR_CLK_FREQ=66666666
Tom Riniafba4112022-06-15 12:03:54 -0400[diff] [blame]52CONFIG_SYS_SPD_BUS_NUM=1
Tom Rini56184602022-02-25 11:19:53 -0500[diff] [blame]53CONFIG_CHIP_SELECTS_PER_CTRL=1
Tom Rini8e99f7d2022-06-15 12:03:55 -0400[diff] [blame]54CONFIG_SYS_DDR_RAW_TIMING=y
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]55CONFIG_SYS_BR0_PRELIM_BOOL=y
56CONFIG_SYS_BR0_PRELIM=0xEF001001
57CONFIG_SYS_OR0_PRELIM=0xFC000FF7
58CONFIG_SYS_BR2_PRELIM_BOOL=y
59CONFIG_SYS_BR2_PRELIM=0xFFB00801
60CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
61CONFIG_SYS_BR3_PRELIM_BOOL=y
62CONFIG_SYS_BR3_PRELIM=0xFFA00801
63CONFIG_SYS_OR3_PRELIM=0xFFF009F7
Tom Rini2c3c2822022-06-06 12:13:29 -0400[diff] [blame]64CONFIG_COMMON_INIT_DDR=y
Tom Rinif8f6b322022-05-21 14:44:28 -0400[diff] [blame]65CONFIG_SPL_COMMON_INIT_DDR=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]66CONFIG_DM_I2C=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]67CONFIG_SPL_SYS_I2C_LEGACY=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]68CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]69CONFIG_SYS_I2C_FSL=y
70CONFIG_SYS_FSL_I2C_OFFSET=0x3000
71CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
72CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]73CONFIG_SYS_I2C_EEPROM_ADDR=0x52
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]74CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]75CONFIG_MTD=y
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]76CONFIG_MTD_NOR_FLASH=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]77CONFIG_FLASH_CFI_DRIVER=y
78CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
Tom Rini302bd672022-07-23 13:04:55 -0400[diff] [blame]79CONFIG_SYS_FLASH_EMPTY_INFO=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]80CONFIG_SYS_FLASH_CFI=y
Tom Rinid38112c2022-07-23 13:05:04 -0400[diff] [blame^]81CONFIG_SYS_MAX_FLASH_SECT=128
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]82CONFIG_DM_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]83CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]84CONFIG_SPI_FLASH_SPANSION=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]85CONFIG_PHY_ATHEROS=y
86CONFIG_PHY_BROADCOM=y
87CONFIG_PHY_DAVICOM=y
88CONFIG_PHY_LXT=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]89CONFIG_PHY_MARVELL=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]90CONFIG_PHY_NATSEMI=y
91CONFIG_PHY_REALTEK=y
92CONFIG_PHY_SMSC=y
93CONFIG_PHY_VITESSE=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]94CONFIG_PHY_FIXED=y
95CONFIG_DM_ETH=y
96CONFIG_DM_MDIO=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]97CONFIG_PHY_GIGE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]98CONFIG_E1000=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]99CONFIG_MII=y
100CONFIG_TSEC_ENET=y
Hou Zhiqiang38853312019-08-27 11:04:11 +0000[diff] [blame]101CONFIG_PCIE_FSL=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]102CONFIG_DM_RTC=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]103CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]104CONFIG_SPI=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]105CONFIG_DM_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]106CONFIG_FSL_ESPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]107CONFIG_USB=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]108CONFIG_USB_EHCI_FSL=y
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]109CONFIG_USB_MAX_CONTROLLER_COUNT=2
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]110CONFIG_USB_STORAGE=y