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stroese9c9acf12003-05-23 11:28:55 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23long int spd_sdram (void);
24
25#include <common.h>
stroese9c9acf12003-05-23 11:28:55 +000026#include <asm/processor.h>
27
28
wdenkda55c6e2004-01-20 23:12:12 +000029int board_early_init_f (void)
stroese9c9acf12003-05-23 11:28:55 +000030{
31 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
32 mtdcr (uicer, 0x00000000); /* disable all ints */
33 mtdcr (uiccr, 0x00000010);
34 mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
35 mtdcr (uictr, 0x00000010); /* set int trigger levels */
36 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
37
38#if 0
39#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
40 /* CS1 */
41 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
42 mtebc (pb1ap, 0x02815480);
43 mtebc (pb1cr, 0xF0018000);
44
45 p = (unsigned int*)0xEF600708;
46 t = *p;
47 t = t | 0x00000400;
48 *p = t;
49
50 /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
51 mtebc (pb2ap, 0x04815A80);
52 mtebc (pb2cr, 0xF0118000);
53
54 /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
55 mtebc (pb3ap, 0x01815280);
56 mtebc (pb3cr, 0xF0218000);
57
58 /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
59 mtebc (pb7ap, 0x01815280);
60 mtebc (pb7cr, 0xF0318000);
61
62
63 /* set UART1 control to select CTS/RTS */
64#define FPGA_BRDC 0xF0300004
65 *(volatile char *) (FPGA_BRDC) |= 0x1;
66
67#endif
68
69 return 0;
70}
71
72
73/* ------------------------------------------------------------------------- */
74
75/*
76 * Check Board Identity:
77 */
78
79int checkboard (void)
80{
81 unsigned char *s = getenv ("serial#");
stroese9c9acf12003-05-23 11:28:55 +000082
stroese5ad6d4d2003-12-09 14:54:43 +000083 puts ("Board: IBM 405EP Eval Board");
stroese9c9acf12003-05-23 11:28:55 +000084
stroese5ad6d4d2003-12-09 14:54:43 +000085 if (s != NULL) {
86 puts (", serial# ");
87 puts (s);
stroese9c9acf12003-05-23 11:28:55 +000088 }
89 putc ('\n');
90
91 return (0);
92}
93
94
95/* -------------------------------------------------------------------------
96 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
97 the necessary info for SDRAM controller configuration
98 ------------------------------------------------------------------------- */
99long int initdram (int board_type)
100{
101 long int ret;
102
103 ret = spd_sdram ();
104 return ret;
105}
106
107/* ------------------------------------------------------------------------- */
108
109int testdram (void)
110{
111 /* TODO: XXX XXX XXX */
112 printf ("test: xxx MB - ok\n");
113
114 return (0);
115}
116
117/* ------------------------------------------------------------------------- */