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git01.mediatek.com / filogic / uboot / d35b4c8f1973f13464589289410c3c7a8a7755bd / . / include / configs / snapper9g45.h
blob: df8ed451a43a49eb59f6c702b79deb309b0e3546 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]2/*
3 * Bluewater Systems Snapper 9G45 module
4 *
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* SoC type is defined in boards.cfg */
14#include <asm/hardware.h>
15#include <linux/sizes.h>
16
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]17/* ARM asynchronous clock */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]18#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
19#define CFG_SYS_AT91_SLOW_CLOCK 32768
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]20
21/* CPU */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]22
23/* SDRAM */
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]24#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
25#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]26#define CFG_SYS_INIT_RAM_SIZE 0x1000
27#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]28
29/* Mem test settings */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]30
31/* NAND Flash */
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]32#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
33#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
34#define CFG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
35#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
36#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]37
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]38/* UARTs/Serial console */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]39
40/* Boot options */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]41
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]42/* Environment settings */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]43
Tom Rinic9edebe2022-12-04 10:03:50 -0500[diff] [blame]44#define CFG_EXTRA_ENV_SETTINGS \
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]45 "ethaddr=00:00:00:00:00:00\0" \
46 "serial=0\0" \
47 "stdout=serial_atmel\0" \
48 "stderr=serial_atmel\0" \
49 "stdin=serial_atmel\0" \
50 "bootlimit=3\0" \
51 "loadaddr=0x71000000\0" \
52 "board_rev=2\0" \
53 "bootfile=/tftpboot/uImage\0" \
54 "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
55 "nfsroot=/export/root\0" \
56 "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
57 "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
58 "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
59 "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
60 "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
61 "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
62 "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
63
64/* Console settings */
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]65
Andre Renaud2369c9c2016-05-05 07:28:22 -0600[diff] [blame]66#endif /* __CONFIG_H */