| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. All rights reserved. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_MT7621_H |
| 9 | #define __CONFIG_MT7621_H |
| 10 | |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 11 | #define CFG_SYS_SDRAM_BASE 0x80000000 |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 12 | |
| Tom Rini | bc9d46b | 2022-12-04 10:04:50 -0500 | [diff] [blame] | 13 | #define CFG_MAX_MEM_MAPPED 0x1c000000 |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 14 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 15 | #define CFG_SYS_INIT_SP_OFFSET 0x800000 |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 16 | |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 17 | /* MMC */ |
| 18 | #define MMC_SUPPORTS_TUNING |
| 19 | |
| 20 | /* NAND */ |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 21 | |
| 22 | /* Serial SPL */ |
| 23 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) |
| Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 24 | #define CFG_SYS_NS16550_CLK 50000000 |
| 25 | #define CFG_SYS_NS16550_COM1 0xbe000c00 |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 26 | #endif |
| 27 | |
| 28 | /* Serial common */ |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 29 | #define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 30 | 230400, 460800, 921600 } |
| 31 | |
| 32 | /* Dummy value */ |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 33 | #define CFG_SYS_UBOOT_BASE 0 |
| developer | 2fddd72 | 2022-05-20 11:22:21 +0800 | [diff] [blame] | 34 | |
| 35 | #endif /* __CONFIG_MT7621_H */ |