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Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09001/*
2 * Configuation settings for the Renesas SH7763RDP board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __SH7763RDP_H
27#define __SH7763RDP_H
28
29#define CONFIG_SH 1
30#define CONFIG_SH4 1
31#define CONFIG_CPU_SH7763 1
32#define CONFIG_SH7763RDP 1
33#define __LITTLE_ENDIAN 1
34
35/*
36 * Command line configuration.
37 */
38#define CONFIG_CMD_SDRAM
39#define CONFIG_CMD_FLASH
40#define CONFIG_CMD_MEMORY
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090041#define CONFIG_CMD_NET
Yoshihiro Shimodac578baa2011-10-31 10:44:18 +090042#define CONFIG_CMD_MII
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090043#define CONFIG_CMD_PING
Mike Frysinger78dcaf42009-01-28 19:08:14 -050044#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090045#define CONFIG_CMD_NFS
46#define CONFIG_CMD_JFFS2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090047
48#define CONFIG_BOOTDELAY -1
49#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
50#define CONFIG_ENV_OVERWRITE 1
51
52#define CONFIG_VERSION_VARIABLE
53#undef CONFIG_SHOW_BOOT_PROGRESS
54
55/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020056#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090057#define CONFIG_BAUDRATE 115200
58#define CONFIG_CONS_SCIF2 1
59
Nobuhiro Iwamatsu69633662011-01-17 20:53:29 +090060#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_LONGHELP /* undef to save memory */
62#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
63#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
64#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
65#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
66#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090067 passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090069 settings for this board */
70
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090071/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
73#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
74#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
75#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090076
77/* Flash(NOR) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020078#define CONFIG_SYS_FLASH_BASE (0xA0000000)
79#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
80#define CONFIG_SYS_MAX_FLASH_BANKS (1)
81#define CONFIG_SYS_MAX_FLASH_SECT (520)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090082
83/* U-boot setting */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
85#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
86#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090087/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090090
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020092#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#undef CONFIG_SYS_FLASH_QUIET_TEST
94#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090095/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090097/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090099/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900101/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900103/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#undef CONFIG_SYS_FLASH_PROTECTION
105#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200106#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200107#define CONFIG_ENV_SECT_SIZE (128 * 1024)
108#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
110/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
111#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200112#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900114
115/* Clock */
116#define CONFIG_SYS_CLK_FREQ 66666666
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200117#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Jean-Christophe PLAGNIOL-VILLARD51704102009-06-04 12:06:47 +0200118#define CONFIG_SYS_HZ 1000
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900119
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +0900120/* Ether */
121#define CONFIG_SH_ETHER 1
122#define CONFIG_SH_ETHER_USE_PORT (1)
123#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
Yoshihiro Shimodac578baa2011-10-31 10:44:18 +0900124#define CONFIG_PHYLIB
125#define CONFIG_BITBANGMII
126#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsu32f900e2012-05-16 10:23:21 +0900127#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +0900128
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900129#endif /* __SH7763RDP_H */