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Andre Schwarz2a293292008-07-09 18:30:44 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#include <version.h>
31
32#define CONFIG_MPC5xxx 1
33#define CONFIG_MPC5200 1
34
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020035#ifndef CONFIG_SYS_TEXT_BASE
36#define CONFIG_SYS_TEXT_BASE 0xFF800000
37#endif
38
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
Andre Schwarz2a293292008-07-09 18:30:44 +020040
Andre Schwarz2a293292008-07-09 18:30:44 +020041#define CONFIG_MISC_INIT_R 1
42
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denkec1067c2008-08-12 14:54:04 +020044#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_CACHELINE_SHIFT 5
Andre Schwarz2a293292008-07-09 18:30:44 +020046#endif
47
48#define CONFIG_PSC_CONSOLE 1
49#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
Andre Schwarz2a293292008-07-09 18:30:44 +020051
52#define CONFIG_PCI 1
53#define CONFIG_PCI_PNP 1
54#undef CONFIG_PCI_SCAN_SHOW
55#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
56
57#define CONFIG_PCI_MEM_BUS 0x40000000
58#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
59#define CONFIG_PCI_MEM_SIZE 0x10000000
60
61#define CONFIG_PCI_IO_BUS 0x50000000
62#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
63#define CONFIG_PCI_IO_SIZE 0x01000000
64
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_XLB_PIPELINING 1
Andre Schwarz2a293292008-07-09 18:30:44 +020066#define CONFIG_HIGH_BATS 1
67
68#define MV_CI mvBlueCOUGAR-P
69#define MV_VCI mvBlueCOUGAR-P
70#define MV_FPGA_DATA 0xff860000
André Schwarza8e1d952009-08-27 14:48:35 +020071#define MV_FPGA_SIZE 0
André Schwarz901f5982009-07-17 14:50:24 +020072#define MV_KERNEL_ADDR 0xffd00000
Andre Schwarz2a293292008-07-09 18:30:44 +020073#define MV_INITRD_ADDR 0xff900000
André Schwarz901f5982009-07-17 14:50:24 +020074#define MV_INITRD_LENGTH 0x00400000
Andre Schwarz2a293292008-07-09 18:30:44 +020075#define MV_SCRATCH_ADDR 0x00000000
76#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
Peter Tyserd78876c2009-09-16 21:38:10 -050077#define MV_SCRIPT_ADDR 0xff840000
78#define MV_SCRIPT_ADDR2 0xff850000
Andre Schwarz2a293292008-07-09 18:30:44 +020079#define MV_DTB_ADDR 0xfffc0000
80
81#define CONFIG_SHOW_BOOT_PROGRESS 1
82
83#define MV_KERNEL_ADDR_RAM 0x00100000
84#define MV_DTB_ADDR_RAM 0x00600000
85#define MV_INITRD_ADDR_RAM 0x01000000
86
87/* pass open firmware flat tree */
88#define CONFIG_OF_LIBFDT 1
89#define CONFIG_OF_BOARD_SETUP 1
90
91#define OF_CPU "PowerPC,5200@0"
92#define OF_SOC "soc5200@f0000000"
93#define OF_TBCLK (bd->bi_busfreq / 4)
94#define MV_DTB_NAME mvbc-p.dtb
95#define CONFIG_OF_STDOUT_VIA_ALIAS 1
96
97/*
98 * Supported commands
99 */
100#include <config_cmd_default.h>
101
102#define CONFIG_CMD_CACHE
103#define CONFIG_CMD_NET
104#define CONFIG_CMD_PING
105#define CONFIG_CMD_DHCP
106#define CONFIG_CMD_SDRAM
107#define CONFIG_CMD_PCI
108#define CONFIG_CMD_FPGA
André Schwarz901f5982009-07-17 14:50:24 +0200109#define CONFIG_CMD_I2C
Andre Schwarz2a293292008-07-09 18:30:44 +0200110
111#undef CONFIG_WATCHDOG
112
113#define CONFIG_BOOTP_VENDOREX
114#define CONFIG_BOOTP_SUBNETMASK
115#define CONFIG_BOOTP_GATEWAY
116#define CONFIG_BOOTP_DNS
117#define CONFIG_BOOTP_DNS2
118#define CONFIG_BOOTP_HOSTNAME
119#define CONFIG_BOOTP_BOOTFILESIZE
120#define CONFIG_BOOTP_BOOTPATH
121#define CONFIG_BOOTP_NTPSERVER
122#define CONFIG_BOOTP_RANDOM_DELAY
123#define CONFIG_BOOTP_SEND_HOSTNAME
124
125/*
126 * Autoboot
127 */
128#define CONFIG_BOOTDELAY 2
129#define CONFIG_AUTOBOOT_KEYED
130#define CONFIG_AUTOBOOT_STOP_STR "s"
131#define CONFIG_ZERO_BOOTDELAY_CHECK
132#define CONFIG_RESET_TO_RETRY 1000
133
Peter Tyserd78876c2009-09-16 21:38:10 -0500134#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
135 then source ${script_addr}; \
136 else source ${script_addr2}; \
Andre Schwarz2a293292008-07-09 18:30:44 +0200137 fi;"
138
139#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
140#define CONFIG_ENV_OVERWRITE
141
Andre Schwarz2a293292008-07-09 18:30:44 +0200142#define CONFIG_EXTRA_ENV_SETTINGS \
143 "console_nr=0\0" \
144 "console=yes\0" \
145 "stdin=serial\0" \
146 "stdout=serial\0" \
147 "stderr=serial\0" \
148 "fpga=0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200149 "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
150 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
151 "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
152 "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
153 "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
154 "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
155 "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
156 "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
157 "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
158 "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
159 "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
160 "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
161 "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
162 "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200163 "mv_version=" U_BOOT_VERSION "\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200164 "dhcp_client_id=" __stringify(MV_CI) "\0" \
165 "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200166 "netretry=no\0" \
167 "use_static_ipaddr=no\0" \
168 "static_ipaddr=192.168.90.10\0" \
169 "static_netmask=255.255.255.0\0" \
170 "static_gateway=0.0.0.0\0" \
171 "initrd_name=uInitrd.mvbc-p-rfs\0" \
172 "zcip=no\0" \
173 "netboot=yes\0" \
174 "mvtest=Ff\0" \
175 "tried_bootfromflash=no\0" \
176 "tried_bootfromnet=no\0" \
177 "use_dhcp=yes\0" \
178 "gev_start=yes\0" \
179 "mvbcdma_debug=0\0" \
180 "mvbcia_debug=0\0" \
181 "propdev_debug=0\0" \
182 "gevss_debug=0\0" \
183 "watchdog=1\0" \
André Schwarz901f5982009-07-17 14:50:24 +0200184 "sensor_cnt=1\0" \
Andre Schwarz2a293292008-07-09 18:30:44 +0200185 ""
186
Andre Schwarz2a293292008-07-09 18:30:44 +0200187/*
188 * IPB Bus clocking configuration.
189 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
191#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Andre Schwarz2a293292008-07-09 18:30:44 +0200192
193/*
194 * Flash configuration
195 */
196#undef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200198#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
200#define CONFIG_SYS_FLASH_EMPTY_INFO
Andre Schwarz2a293292008-07-09 18:30:44 +0200201
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
203#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
Andre Schwarz2a293292008-07-09 18:30:44 +0200204
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_MAX_FLASH_BANKS 1
206#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarz2a293292008-07-09 18:30:44 +0200207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_LOWBOOT
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200209#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_SIZE 0x00800000
Andre Schwarz2a293292008-07-09 18:30:44 +0200211
212/*
213 * Environment settings
214 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200215#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz2a293292008-07-09 18:30:44 +0200217
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200218#define CONFIG_ENV_ADDR 0xFFFE0000
219#define CONFIG_ENV_SIZE 0x10000
220#define CONFIG_ENV_SECT_SIZE 0x10000
221#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
222#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200223
224/*
225 * Memory map
226 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_MBAR 0xF0000000
228#define CONFIG_SYS_SDRAM_BASE 0x00000000
229#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Andre Schwarz2a293292008-07-09 18:30:44 +0200230
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200232#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200233
Wolfgang Denk0191e472010-10-26 14:34:52 +0200234#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarz2a293292008-07-09 18:30:44 +0200236
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200237#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
239#define CONFIG_SYS_RAMBOOT 1
Andre Schwarz2a293292008-07-09 18:30:44 +0200240#endif
241
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
243#define CONFIG_SYS_MONITOR_LEN (512 << 10)
244#define CONFIG_SYS_MALLOC_LEN (512 << 10)
245#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Andre Schwarz2a293292008-07-09 18:30:44 +0200246
247/*
André Schwarz901f5982009-07-17 14:50:24 +0200248 * I2C configuration
249 */
250#define CONFIG_HARD_I2C 1
251#define CONFIG_SYS_I2C_MODULE 1
252#define CONFIG_SYS_I2C_SPEED 86000
253#define CONFIG_SYS_I2C_SLAVE 0x7F
254
255/*
Andre Schwarz2a293292008-07-09 18:30:44 +0200256 * Ethernet configuration
257 */
Andre Schwarz2a293292008-07-09 18:30:44 +0200258#define CONFIG_NET_RETRY_COUNT 5
259
260#define CONFIG_E1000
Wolfgang Denk9a0882b2008-07-31 13:57:20 +0200261#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
Andre Schwarz2a293292008-07-09 18:30:44 +0200262#undef CONFIG_MPC5xxx_FEC
263#undef CONFIG_PHY_ADDR
264#define CONFIG_NETDEV eth0
265
266/*
267 * Miscellaneous configurable options
268 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200269#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz2a293292008-07-09 18:30:44 +0200270#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271#undef CONFIG_SYS_LONGHELP
272#define CONFIG_SYS_PROMPT "=> "
Wolfgang Denkec1067c2008-08-12 14:54:04 +0200273#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_CBSIZE 1024
Andre Schwarz2a293292008-07-09 18:30:44 +0200275#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_CBSIZE 256
Andre Schwarz2a293292008-07-09 18:30:44 +0200277#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
279#define CONFIG_SYS_MAXARGS 16
280#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200281
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_MEMTEST_START 0x00800000
283#define CONFIG_SYS_MEMTEST_END 0x02f00000
Andre Schwarz2a293292008-07-09 18:30:44 +0200284
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_HZ 1000
Andre Schwarz2a293292008-07-09 18:30:44 +0200286
287/* default load address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#define CONFIG_SYS_LOAD_ADDR 0x02000000
Andre Schwarz2a293292008-07-09 18:30:44 +0200289/* default location for tftp and bootm */
290#define CONFIG_LOADADDR 0x00200000
291
292/*
293 * Various low-level settings
294 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
Andre Schwarz2a293292008-07-09 18:30:44 +0200296
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
298#define CONFIG_SYS_HID0_FINAL HID0_ICE
Andre Schwarz2a293292008-07-09 18:30:44 +0200299
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200300#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
301#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
302#define CONFIG_SYS_BOOTCS_CFG 0x00047800
303#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
304#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Andre Schwarz2a293292008-07-09 18:30:44 +0200305
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200306#define CONFIG_SYS_CS_BURST 0x000000f0
307#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
Andre Schwarz2a293292008-07-09 18:30:44 +0200308
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_RESET_ADDRESS 0x00000100
Andre Schwarz2a293292008-07-09 18:30:44 +0200310
311#undef FPGA_DEBUG
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
313#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
Andre Schwarz2a293292008-07-09 18:30:44 +0200314#define CONFIG_FPGA_ALTERA 1
315#define CONFIG_FPGA_CYCLON2 1
316#define CONFIG_FPGA_COUNT 1
317
318#endif