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Andre Schwarzc82fdea2011-04-14 15:11:44 +02001Matrix Vision MergerBox
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41. Board Description
5
6 The MergerBox is a 120x160mm single board computing platform
7 for 3D Full-HD digital video processing.
8
9 Power Supply is 10-32VDC.
10
112 System Components
12
132.1 CPU
14 Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
15 256 MByte DDR-II memory @ 333MHz data rate.
16 64 MByte Nor Flash on local bus.
17 1 GByte Nand Flash on FCM.
18 1 Vitesse VSC8601 RGMII ethernet Phys.
19 1 USB host controller over ULPI I/F with 4-Port hub.
20 2 serial ports. Console running on ttyS0 @ 115200 8N1.
21 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
22 2 PCIe x1 busses on local mPCIe and cutom expansion connector.
23 2 SATA host ports.
24 System configuration (HRCW) is taken from I2C EEPROM.
25
262.2 Graphics
27 SM107 emebedded video controller driving a 5" 800x480 TFT panel.
28 Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
29
302.3 FPGA
31 Altera Cyclone-IV EP4C115 with several PCI DMA engines.
32 Connects to 7x Gennum 3G-SDI transceivers as video interconnect
33 as well as a HDMI v1.4 compliant output for 3D monitoring.
34 Utilizes two more DDR-II controllers providing 256MB memory.
35
362.4 I2C
37 Bus1:
38 AD7418 @ 0x50 for voltage/temp. monitoring.
39 SX8650 @ 0x90 touch controller for HMI.
40 EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
41 Bus2:
42 mPCIe SMBus
43 SiI9022A @ 0x72/0xC0 HDMI transmitter.
44 TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
45 LMH1983 @ 0xCA video PLL.
46 DS1338C @ 0xD0 real-time clock with embedded crystal.
47 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
48
493 Flash layout.
50
51 reset vector is 0x00000100, i.e. low boot.
52
53 00000000 u-boot binary.
54 00100000 FPGA raw bit file.
55 00300000 FIT image holding kernel, dtb and rescue squashfs.
56 03d00000 u-boot environment.
57 03e00000 splash image
58
59 mtd partitions are propagated to linux kernel via device tree blob.