Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| 2 | /* |
| 3 | * Copyright 2021-2022 Marek Vasut <marex@denx.de> |
| 4 | */ |
| 5 | |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 6 | /dts-v1/; |
| 7 | |
| 8 | #include "imx8mm-verdin.dtsi" |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 9 | |
| 10 | / { |
| 11 | model = "MENLO MX8MM EMBEDDED DEVICE"; |
| 12 | compatible = "menlo,mx8menlo", |
| 13 | "toradex,verdin-imx8mm", |
| 14 | "fsl,imx8mm"; |
| 15 | |
| 16 | /delete-node/ gpio-keys; |
| 17 | |
| 18 | leds { |
| 19 | compatible = "gpio-leds"; |
| 20 | pinctrl-names = "default"; |
| 21 | pinctrl-0 = <&pinctrl_led>; |
| 22 | |
Marcel Ziswiler | 6dd051a | 2022-11-07 22:22:41 +0100 | [diff] [blame] | 23 | led-1 { |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 24 | label = "TestLed601"; |
| 25 | gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; |
| 26 | linux,default-trigger = "mmc0"; |
| 27 | }; |
| 28 | |
Marcel Ziswiler | 6dd051a | 2022-11-07 22:22:41 +0100 | [diff] [blame] | 29 | led-2 { |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 30 | label = "TestLed602"; |
| 31 | gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; |
| 32 | linux,default-trigger = "heartbeat"; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | beeper { |
| 37 | compatible = "gpio-beeper"; |
| 38 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&pinctrl_beeper>; |
| 40 | gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; |
| 41 | }; |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 42 | |
| 43 | /* Fixed clock dedicated to SPI CAN on carrier board */ |
| 44 | clk_xtal20: clk-xtal20 { |
| 45 | compatible = "fixed-clock"; |
| 46 | #clock-cells = <0>; |
| 47 | clock-frequency = <20000000>; |
| 48 | }; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | &ecspi1 { |
| 52 | #address-cells = <1>; |
| 53 | #size-cells = <0>; |
| 54 | pinctrl-names = "default"; |
| 55 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 56 | cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| 57 | status = "okay"; |
| 58 | |
| 59 | /* CAN controller on the baseboard */ |
| 60 | canfd: can@0 { |
| 61 | compatible = "microchip,mcp2518fd"; |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 62 | clocks = <&clk_xtal20>; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 63 | interrupt-parent = <&gpio1>; |
| 64 | interrupts = <8 IRQ_TYPE_EDGE_FALLING>; |
| 65 | reg = <0>; |
| 66 | spi-max-frequency = <2000000>; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | }; |
| 70 | |
| 71 | &ecspi2 { |
| 72 | pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>; |
| 73 | cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>; |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 74 | status = "okay"; |
| 75 | |
| 76 | spidev@0 { |
| 77 | compatible = "menlo,m53cpld"; |
| 78 | reg = <0>; |
| 79 | spi-max-frequency = <25000000>; |
| 80 | }; |
| 81 | |
| 82 | spidev@1 { |
| 83 | compatible = "menlo,m53cpld"; |
| 84 | reg = <1>; |
| 85 | spi-max-frequency = <25000000>; |
| 86 | }; |
| 87 | |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | ðphy0 { |
| 91 | max-speed = <100>; |
| 92 | }; |
| 93 | |
| 94 | &fec1 { |
| 95 | status = "okay"; |
| 96 | }; |
| 97 | |
| 98 | &flexspi { |
| 99 | status = "okay"; |
| 100 | |
| 101 | flash@0 { |
| 102 | reg = <0>; |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <1>; |
| 105 | compatible = "jedec,spi-nor"; |
| 106 | spi-max-frequency = <66000000>; |
| 107 | spi-rx-bus-width = <4>; |
| 108 | spi-tx-bus-width = <4>; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | &gpio1 { |
| 113 | gpio-line-names = |
| 114 | "", "", "", "", |
| 115 | "", "", "", "", |
| 116 | "", "", "", "", |
| 117 | "", "", "", "", |
| 118 | "", "", "", "", |
| 119 | "", "", "", "", |
| 120 | "", "", "", "", |
| 121 | "", "", "", ""; |
| 122 | }; |
| 123 | |
| 124 | &gpio2 { |
| 125 | gpio-line-names = |
| 126 | "", "", "", "", |
| 127 | "", "", "", "", |
| 128 | "", "", "", "", |
| 129 | "", "", "", "", |
| 130 | "", "", "", "", |
| 131 | "", "", "", "", |
| 132 | "", "", "", "", |
| 133 | "", "", "", ""; |
| 134 | }; |
| 135 | |
| 136 | &gpio3 { |
| 137 | gpio-line-names = |
| 138 | "", "", "", "", |
| 139 | "", "", "", "", |
| 140 | "", "", "", "", |
| 141 | "", "", "", "", |
| 142 | "", "", "", "", |
| 143 | "", "", "DISP_reset", "KBD_intI", |
| 144 | "", "", "", "", |
| 145 | "", "", "", ""; |
| 146 | }; |
| 147 | |
| 148 | &gpio4 { |
| 149 | /* |
| 150 | * CPLD_D[n] is ARM_CPLD[n] in schematic |
| 151 | * CPLD_int is SA_INTERRUPT in schematic |
| 152 | * CPLD_reset is RESET_SOFT in schematic |
| 153 | */ |
| 154 | gpio-line-names = |
Marcel Ziswiler | 6dd051a | 2022-11-07 22:22:41 +0100 | [diff] [blame] | 155 | "CPLD_D[6]", "CPLD_int", "CPLD_reset", "", |
| 156 | "", "CPLD_D[7]", "", "", |
| 157 | "", "", "", "CPLD_D[5]", |
| 158 | "CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]", |
| 159 | "CPLD_D[0]", "", "", "", |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 160 | "", "", "", "", |
| 161 | "", "", "", "KBD_intK", |
| 162 | "", "", "", ""; |
| 163 | }; |
| 164 | |
| 165 | &gpio5 { |
| 166 | gpio-line-names = |
| 167 | "", "", "", "", |
| 168 | "", "", "", "", |
| 169 | "", "", "", "", |
| 170 | "", "", "", "", |
| 171 | "", "", "", "", |
| 172 | "", "", "", "", |
| 173 | "", "", "", "", |
| 174 | "", "", "", ""; |
| 175 | }; |
| 176 | |
| 177 | &gpio_expander_21 { |
| 178 | status = "okay"; |
| 179 | }; |
| 180 | |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 181 | &hwmon { |
| 182 | status = "okay"; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 183 | }; |
| 184 | |
| 185 | &i2c3 { |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 186 | status = "okay"; |
| 187 | }; |
| 188 | |
| 189 | &i2c4 { |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 190 | /* None of this is present on the SoM. */ |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 191 | /delete-node/ bridge@2c; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 192 | /delete-node/ hdmi@48; |
| 193 | /delete-node/ touch@4a; |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 194 | /delete-node/ sensor@4f; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 195 | /delete-node/ eeprom@50; |
| 196 | /delete-node/ eeprom@57; |
| 197 | }; |
| 198 | |
| 199 | &iomuxc { |
| 200 | pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>, |
| 201 | <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; |
| 202 | |
| 203 | pinctrl_beeper: beepergrp { |
| 204 | fsl,pins = < |
| 205 | MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4 |
| 206 | >; |
| 207 | }; |
| 208 | |
| 209 | pinctrl_ecspi1: ecspi1grp { |
| 210 | fsl,pins = < |
| 211 | MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4 |
| 212 | MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4 |
| 213 | MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4 |
| 214 | MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4 |
| 215 | >; |
| 216 | }; |
| 217 | |
| 218 | pinctrl_led: ledgrp { |
| 219 | fsl,pins = < |
| 220 | MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 |
| 221 | MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 |
| 222 | >; |
| 223 | }; |
| 224 | |
| 225 | pinctrl_uart4_rts: uart4rtsgrp { |
| 226 | fsl,pins = < |
| 227 | /* SODIMM 222 */ |
| 228 | MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 |
| 229 | >; |
| 230 | }; |
| 231 | }; |
| 232 | |
| 233 | &pinctrl_gpio1 { |
| 234 | fsl,pins = < |
| 235 | /* SODIMM 206 */ |
| 236 | MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4 |
| 237 | >; |
| 238 | }; |
| 239 | |
| 240 | &pinctrl_gpio_hog1 { |
| 241 | fsl,pins = < |
| 242 | /* SODIMM 88 */ |
| 243 | MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 |
| 244 | /* CPLD_int */ |
| 245 | MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 |
| 246 | /* CPLD_reset */ |
| 247 | MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 |
| 248 | /* SODIMM 94 */ |
| 249 | MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 |
| 250 | /* SODIMM 96 */ |
| 251 | MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 |
| 252 | /* CPLD_D[7] */ |
| 253 | MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 |
| 254 | /* CPLD_D[6] */ |
| 255 | MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 |
| 256 | /* CPLD_D[5] */ |
| 257 | MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 |
| 258 | /* CPLD_D[4] */ |
| 259 | MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 |
| 260 | /* CPLD_D[3] */ |
| 261 | MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 |
| 262 | /* CPLD_D[2] */ |
| 263 | MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 |
| 264 | /* CPLD_D[1] */ |
| 265 | MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 |
| 266 | /* CPLD_D[0] */ |
| 267 | MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 |
| 268 | /* KBD_intK */ |
| 269 | MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4 |
| 270 | /* DISP_reset */ |
| 271 | MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4 |
| 272 | /* KBD_intI */ |
| 273 | MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4 |
| 274 | /* SODIMM 46 */ |
| 275 | MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4 |
| 276 | >; |
| 277 | }; |
| 278 | |
| 279 | &pinctrl_uart1 { |
| 280 | fsl,pins = < |
| 281 | /* SODIMM 149 */ |
| 282 | MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 |
| 283 | /* SODIMM 147 */ |
| 284 | MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 |
| 285 | /* SODIMM 210 */ |
| 286 | MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4 |
| 287 | /* SODIMM 212 */ |
| 288 | MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4 |
| 289 | >; |
| 290 | }; |
| 291 | |
| 292 | ®_usb_otg1_vbus { |
| 293 | /delete-property/ enable-active-high; |
| 294 | gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; |
| 295 | }; |
| 296 | |
| 297 | ®_usb_otg2_vbus { |
| 298 | /delete-property/ enable-active-high; |
| 299 | gpio = <&gpio1 14 GPIO_ACTIVE_LOW>; |
| 300 | }; |
| 301 | |
| 302 | &sai2 { |
| 303 | status = "disabled"; |
| 304 | }; |
| 305 | |
| 306 | &uart1 { |
| 307 | uart-has-rtscts; |
| 308 | status = "okay"; |
| 309 | }; |
| 310 | |
| 311 | &uart2 { |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 312 | status = "okay"; |
| 313 | }; |
| 314 | |
| 315 | &uart4 { |
| 316 | pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>; |
| 317 | linux,rs485-enabled-at-boot-time; |
| 318 | rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| 319 | status = "okay"; |
| 320 | }; |
| 321 | |
| 322 | &usbotg1 { |
Marcel Ziswiler | ca453f2 | 2022-07-21 15:27:40 +0200 | [diff] [blame] | 323 | dr_mode = "peripheral"; |
Marek Vasut | e762875 | 2022-04-08 02:15:01 +0200 | [diff] [blame] | 324 | status = "okay"; |
| 325 | }; |
| 326 | |
| 327 | &usbotg2 { |
| 328 | dr_mode = "host"; |
| 329 | status = "okay"; |
| 330 | }; |
| 331 | |
| 332 | &usdhc2 { |
| 333 | status = "okay"; |
| 334 | }; |