rev13@wp.pl | fec465a | 2015-03-01 12:44:40 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 |
Kamil Lulko | decd33b | 2015-11-29 11:50:53 +0100 | [diff] [blame] | 3 | * Kamil Lulko, <kamil.lulko@gmail.com> |
rev13@wp.pl | fec465a | 2015-03-01 12:44:40 +0100 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Patrice Chotard | d11d391 | 2017-11-15 13:14:53 +0100 | [diff] [blame] | 9 | #include <stm32_rcc.h> |
rev13@wp.pl | fec465a | 2015-03-01 12:44:40 +0100 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | #include <asm/armv7m.h> |
| 12 | #include <asm/arch/stm32.h> |
| 13 | |
| 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
| 16 | #define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000) |
| 17 | |
| 18 | #define RCC_APB1ENR_TIM2EN (1 << 0) |
| 19 | |
| 20 | struct stm32_tim2_5 { |
| 21 | u32 cr1; |
| 22 | u32 cr2; |
| 23 | u32 smcr; |
| 24 | u32 dier; |
| 25 | u32 sr; |
| 26 | u32 egr; |
| 27 | u32 ccmr1; |
| 28 | u32 ccmr2; |
| 29 | u32 ccer; |
| 30 | u32 cnt; |
| 31 | u32 psc; |
| 32 | u32 arr; |
| 33 | u32 reserved1; |
| 34 | u32 ccr1; |
| 35 | u32 ccr2; |
| 36 | u32 ccr3; |
| 37 | u32 ccr4; |
| 38 | u32 reserved2; |
| 39 | u32 dcr; |
| 40 | u32 dmar; |
| 41 | u32 or; |
| 42 | }; |
| 43 | |
| 44 | #define TIM_CR1_CEN (1 << 0) |
| 45 | |
| 46 | #define TIM_EGR_UG (1 << 0) |
| 47 | |
| 48 | int timer_init(void) |
| 49 | { |
| 50 | struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; |
| 51 | |
| 52 | setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); |
| 53 | |
Patrice Chotard | d2bc05c7 | 2017-12-12 09:49:38 +0100 | [diff] [blame^] | 54 | writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1, |
| 55 | &tim->psc); |
rev13@wp.pl | fec465a | 2015-03-01 12:44:40 +0100 | [diff] [blame] | 56 | |
| 57 | writel(0xFFFFFFFF, &tim->arr); |
| 58 | writel(TIM_CR1_CEN, &tim->cr1); |
| 59 | setbits_le32(&tim->egr, TIM_EGR_UG); |
| 60 | |
| 61 | gd->arch.tbl = 0; |
| 62 | gd->arch.tbu = 0; |
| 63 | gd->arch.lastinc = 0; |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | ulong get_timer(ulong base) |
| 69 | { |
| 70 | return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base; |
| 71 | } |
| 72 | |
| 73 | unsigned long long get_ticks(void) |
| 74 | { |
| 75 | struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; |
| 76 | u32 now; |
| 77 | |
| 78 | now = readl(&tim->cnt); |
| 79 | |
| 80 | if (now >= gd->arch.lastinc) |
| 81 | gd->arch.tbl += (now - gd->arch.lastinc); |
| 82 | else |
| 83 | gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; |
| 84 | |
| 85 | gd->arch.lastinc = now; |
| 86 | |
| 87 | return gd->arch.tbl; |
| 88 | } |
| 89 | |
| 90 | void reset_timer(void) |
| 91 | { |
| 92 | struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; |
| 93 | |
| 94 | gd->arch.lastinc = readl(&tim->cnt); |
| 95 | gd->arch.tbl = 0; |
| 96 | } |
| 97 | |
| 98 | /* delay x useconds */ |
| 99 | void __udelay(ulong usec) |
| 100 | { |
| 101 | unsigned long long start; |
| 102 | |
| 103 | start = get_ticks(); /* get current timestamp */ |
| 104 | while ((get_ticks() - start) < usec) |
| 105 | ; /* loop till time has passed */ |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | * This function is derived from PowerPC code (timebase clock frequency). |
| 110 | * On ARM it returns the number of timer ticks per second. |
| 111 | */ |
| 112 | ulong get_tbclk(void) |
| 113 | { |
| 114 | return CONFIG_SYS_HZ_CLOCK; |
| 115 | } |