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Stefano Babic421834e2010-02-05 15:13:58 +01001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the MX51EVK Board
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic421834e2010-02-05 15:13:58 +01009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Stefano Babic421834e2010-02-05 15:13:58 +010014 /* High Level Configuration Options */
15
Gong Qianyu52de2e52015-10-26 19:47:42 +080016#define CONFIG_SYS_FSL_CLK
Stefano Babic9fb39692011-01-24 00:14:27 +000017#define CONFIG_SYS_TEXT_BASE 0x97800000
18
Liu Hui-R64343baa2d782011-01-03 22:27:35 +000019#include <asm/arch/imx-regs.h>
Stefano Babic421834e2010-02-05 15:13:58 +010020
Fabio Estevam6f2901a2011-10-24 08:24:28 +000021#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Fabio Estevam6f2901a2011-10-24 08:24:28 +000022#define CONFIG_SETUP_MEMORY_TAGS
23#define CONFIG_INITRD_TAG
Benoît Thébaudeau7477d112012-09-18 04:48:42 +000024#define CONFIG_REVISION_TAG
Stefano Babic421834e2010-02-05 15:13:58 +010025
Fabio Estevam1b9c57a2011-09-22 08:07:18 +000026#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
Stefano Babic421834e2010-02-05 15:13:58 +010027/*
28 * Size of malloc() pool
29 */
Fabio Estevam12ba8602012-05-09 06:39:41 +000030#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Stefano Babic421834e2010-02-05 15:13:58 +010031
32/*
33 * Hardware drivers
34 */
Benoît Thébaudeau4490eab2013-04-23 10:17:43 +000035#define CONFIG_FSL_IIM
Benoît Thébaudeau4490eab2013-04-23 10:17:43 +000036
Stefano Babic421834e2010-02-05 15:13:58 +010037#define CONFIG_MXC_UART
Stefano Babic1ca47d92011-11-22 15:22:39 +010038#define CONFIG_MXC_UART_BASE UART1_BASE
Stefano Babic57008812011-08-21 23:29:52 +020039#define CONFIG_MXC_GPIO
Stefano Babic421834e2010-02-05 15:13:58 +010040
41/*
Stefano Babic96651272010-03-16 17:22:21 +010042 * SPI Configs
43 * */
Stefano Babic96651272010-03-16 17:22:21 +010044
45#define CONFIG_MXC_SPI
46
Stefano Babicdba2efc2011-10-08 10:59:20 +020047/* PMIC Controller */
Łukasz Majewski1b6d9ed2012-11-13 03:22:14 +000048#define CONFIG_POWER
49#define CONFIG_POWER_SPI
50#define CONFIG_POWER_FSL
Stefano Babic96651272010-03-16 17:22:21 +010051#define CONFIG_FSL_PMIC_BUS 0
52#define CONFIG_FSL_PMIC_CS 0
53#define CONFIG_FSL_PMIC_CLK 2500000
Stefano Babic4c596992010-08-23 20:41:19 +020054#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babicdba2efc2011-10-08 10:59:20 +020055#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevamb5558552011-10-24 06:44:16 +000056#define CONFIG_RTC_MC13XXX
Stefano Babic96651272010-03-16 17:22:21 +010057
58/*
Stefano Babic421834e2010-02-05 15:13:58 +010059 * MMC Configs
60 * */
61#define CONFIG_FSL_ESDHC
Fabio Estevame61224a2014-09-16 20:03:40 -030062#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
Stefano Babic421834e2010-02-05 15:13:58 +010063#define CONFIG_SYS_FSL_ESDHC_NUM 2
64
Stefano Babic421834e2010-02-05 15:13:58 +010065/*
66 * Eth Configs
67 */
Stefano Babic421834e2010-02-05 15:13:58 +010068#define CONFIG_MII
Stefano Babic421834e2010-02-05 15:13:58 +010069
70#define CONFIG_FEC_MXC
71#define IMX_FEC_BASE FEC_BASE_ADDR
72#define CONFIG_FEC_MXC_PHYADDR 0x1F
73
Wolfgang Grandegger2e865da2011-11-11 14:03:38 +010074/* USB Configs */
Wolfgang Grandegger2e865da2011-11-11 14:03:38 +010075#define CONFIG_USB_EHCI_MX5
Wolfgang Grandegger2e865da2011-11-11 14:03:38 +010076#define CONFIG_MXC_USB_PORT 1
77#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
78#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
79
Fabio Estevam12ba8602012-05-09 06:39:41 +000080/* Framebuffer and LCD */
81#define CONFIG_PREBOOT
Fabio Estevamc6dd2e02012-05-31 07:23:56 +000082#define CONFIG_VIDEO_IPUV3
Fabio Estevam12ba8602012-05-09 06:39:41 +000083#define CONFIG_VIDEO_BMP_RLE8
84#define CONFIG_SPLASH_SCREEN
85#define CONFIG_BMP_16BPP
86#define CONFIG_VIDEO_LOGO
Fabio Estevam82692e22012-05-31 07:24:00 +000087#define CONFIG_IPUV3_CLK 133000000
Fabio Estevam12ba8602012-05-09 06:39:41 +000088
Stefano Babic421834e2010-02-05 15:13:58 +010089/* allow to overwrite serial and ethaddr */
90#define CONFIG_ENV_OVERWRITE
91#define CONFIG_CONS_INDEX 1
Stefano Babic421834e2010-02-05 15:13:58 +010092
Wolfgang Grandegger96529e22011-10-17 08:21:56 +000093#define CONFIG_ETHPRIME "FEC0"
Stefano Babic421834e2010-02-05 15:13:58 +010094
Fabio Estevam1f170172013-04-19 11:04:36 +000095#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
Stefano Babic421834e2010-02-05 15:13:58 +010096
Shawn Guo62679bb2010-10-25 23:20:30 +080097#define CONFIG_EXTRA_ENV_SETTINGS \
98 "script=boot.scr\0" \
Otavio Salvador22af2cf2014-01-16 19:58:00 -020099 "image=zImage\0" \
Fabio Estevam1f170172013-04-19 11:04:36 +0000100 "fdt_file=imx51-babbage.dtb\0" \
101 "fdt_addr=0x91000000\0" \
102 "boot_fdt=try\0" \
103 "ip_dyn=yes\0" \
Shawn Guo62679bb2010-10-25 23:20:30 +0800104 "mmcdev=0\0" \
Otavio Salvador1c1a5192013-06-28 18:52:43 -0300105 "mmcpart=1\0" \
106 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
Shawn Guo62679bb2010-10-25 23:20:30 +0800107 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
Fabio Estevam107d0b42013-04-19 11:04:37 +0000108 "root=${mmcroot}\0" \
Shawn Guo62679bb2010-10-25 23:20:30 +0800109 "loadbootscript=" \
110 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
111 "bootscript=echo Running bootscript from mmc ...; " \
112 "source\0" \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200113 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
Fabio Estevam1f170172013-04-19 11:04:36 +0000114 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
Shawn Guo62679bb2010-10-25 23:20:30 +0800115 "mmcboot=echo Booting from mmc ...; " \
116 "run mmcargs; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000117 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
118 "if run loadfdt; then " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200119 "bootz ${loadaddr} - ${fdt_addr}; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000120 "else " \
121 "if test ${boot_fdt} = try; then " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200122 "bootz; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000123 "else " \
124 "echo WARN: Cannot load the DT; " \
125 "fi; " \
126 "fi; " \
127 "else " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200128 "bootz; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000129 "fi;\0" \
Shawn Guo62679bb2010-10-25 23:20:30 +0800130 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
131 "root=/dev/nfs " \
132 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
133 "netboot=echo Booting from net ...; " \
134 "run netargs; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000135 "if test ${ip_dyn} = yes; then " \
136 "setenv get_cmd dhcp; " \
137 "else " \
138 "setenv get_cmd tftp; " \
139 "fi; " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200140 "${get_cmd} ${image}; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000141 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
142 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200143 "bootz ${loadaddr} - ${fdt_addr}; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000144 "else " \
145 "if test ${boot_fdt} = try; then " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200146 "bootz; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000147 "else " \
148 "echo ERROR: Cannot load the DT; " \
149 "exit; " \
150 "fi; " \
151 "fi; " \
152 "else " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200153 "bootz; " \
Fabio Estevam1f170172013-04-19 11:04:36 +0000154 "fi;\0"
Shawn Guo62679bb2010-10-25 23:20:30 +0800155
156#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +0000157 "mmc dev ${mmcdev}; if mmc rescan; then " \
Shawn Guo62679bb2010-10-25 23:20:30 +0800158 "if run loadbootscript; then " \
159 "run bootscript; " \
160 "else " \
Otavio Salvador22af2cf2014-01-16 19:58:00 -0200161 "if run loadimage; then " \
Shawn Guo62679bb2010-10-25 23:20:30 +0800162 "run mmcboot; " \
163 "else run netboot; " \
164 "fi; " \
165 "fi; " \
166 "else run netboot; fi"
Stefano Babic421834e2010-02-05 15:13:58 +0100167
168#define CONFIG_ARP_TIMEOUT 200UL
169
170/*
171 * Miscellaneous configurable options
172 */
173#define CONFIG_SYS_LONGHELP /* undef to save memory */
Stefano Babic421834e2010-02-05 15:13:58 +0100174#define CONFIG_AUTO_COMPLETE
Stefano Babic421834e2010-02-05 15:13:58 +0100175
176#define CONFIG_SYS_MEMTEST_START 0x90000000
Fabio Estevame4bd14e2012-02-09 14:25:08 +0000177#define CONFIG_SYS_MEMTEST_END 0x90010000
Stefano Babic421834e2010-02-05 15:13:58 +0100178
179#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
180
Stefano Babic421834e2010-02-05 15:13:58 +0100181#define CONFIG_CMDLINE_EDITING
182
183/*-----------------------------------------------------------------------
Stefano Babic421834e2010-02-05 15:13:58 +0100184 * Physical Memory Map
185 */
186#define CONFIG_NR_DRAM_BANKS 1
187#define PHYS_SDRAM_1 CSD0_BASE_ADDR
188#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
189
Shawn Guobc08e7e2010-10-28 10:13:15 +0800190#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
191#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
192#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
193
194#define CONFIG_SYS_INIT_SP_OFFSET \
195 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196#define CONFIG_SYS_INIT_SP_ADDR \
197 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
198
Stefano Babic0c3d8ee2010-03-28 13:43:26 +0200199#define CONFIG_SYS_DDR_CLKSEL 0
200#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
Benoît Thébaudeauaa2bcc22012-11-05 10:07:04 +0000201#define CONFIG_SYS_MAIN_PWR_ON
Stefano Babic0c3d8ee2010-03-28 13:43:26 +0200202
Stefano Babic421834e2010-02-05 15:13:58 +0100203/*-----------------------------------------------------------------------
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900204 * environment organization
Stefano Babic421834e2010-02-05 15:13:58 +0100205 */
Jason Liud5fcf032010-11-17 16:01:18 +0800206#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
207#define CONFIG_ENV_SIZE (8 * 1024)
Jason Liud5fcf032010-11-17 16:01:18 +0800208#define CONFIG_SYS_MMC_ENV_DEV 0
Stefano Babic421834e2010-02-05 15:13:58 +0100209
Stefano Babic421834e2010-02-05 15:13:58 +0100210#endif