Ashish Kumar | 227b4bc | 2017-08-31 16:12:54 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2017 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __LS1088_COMMON_H |
| 8 | #define __LS1088_COMMON_H |
| 9 | |
| 10 | |
| 11 | #define CONFIG_REMAKE_ELF |
| 12 | #define CONFIG_FSL_LAYERSCAPE |
| 13 | #define CONFIG_MP |
| 14 | |
| 15 | #include <asm/arch/stream_id_lsch3.h> |
| 16 | #include <asm/arch/config.h> |
| 17 | #include <asm/arch/soc.h> |
| 18 | |
| 19 | /* Link Definitions */ |
| 20 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) |
| 21 | |
| 22 | /* Link Definitions */ |
| 23 | #ifdef CONFIG_QSPI_BOOT |
| 24 | #define CONFIG_SYS_TEXT_BASE 0x20100000 |
| 25 | #else |
| 26 | #define CONFIG_SYS_TEXT_BASE 0x30100000 |
| 27 | #endif |
| 28 | |
| 29 | #define CONFIG_SUPPORT_RAW_INITRD |
| 30 | |
| 31 | |
| 32 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 33 | |
| 34 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
| 35 | |
| 36 | #define CONFIG_VERY_BIG_RAM |
| 37 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
| 38 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
| 39 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 40 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL |
| 41 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 |
| 42 | /* |
| 43 | * SMP Definitinos |
| 44 | */ |
| 45 | #define CPU_RELEASE_ADDR secondary_boot_func |
| 46 | |
| 47 | /* Size of malloc() pool */ |
| 48 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) |
| 49 | |
| 50 | /* I2C */ |
| 51 | #define CONFIG_SYS_I2C |
| 52 | #define CONFIG_SYS_I2C_MXC |
| 53 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 54 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
| 55 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
| 56 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ |
| 57 | |
| 58 | /* Serial Port */ |
| 59 | #define CONFIG_CONS_INDEX 1 |
| 60 | #define CONFIG_SYS_NS16550_SERIAL |
| 61 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 62 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) |
| 63 | |
| 64 | #define CONFIG_BAUDRATE 115200 |
| 65 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 66 | |
| 67 | /* IFC */ |
| 68 | #define CONFIG_FSL_IFC |
| 69 | |
| 70 | /* |
| 71 | * During booting, IFC is mapped at the region of 0x30000000. |
| 72 | * But this region is limited to 256MB. To accommodate NOR, promjet |
| 73 | * and FPGA. This region is divided as below: |
| 74 | * 0x30000000 - 0x37ffffff : 128MB : NOR flash |
| 75 | * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet |
| 76 | * 0x3C000000 - 0x40000000 : 64MB : FPGA etc |
| 77 | * |
| 78 | * To accommodate bigger NOR flash and other devices, we will map IFC |
| 79 | * chip selects to as below: |
| 80 | * 0x5_1000_0000..0x5_1fff_ffff Memory Hole |
| 81 | * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) |
| 82 | * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB |
| 83 | * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) |
| 84 | * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) |
| 85 | * |
| 86 | * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. |
| 87 | * CONFIG_SYS_FLASH_BASE has the final address (core view) |
| 88 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) |
| 89 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address |
| 90 | * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting |
| 91 | */ |
| 92 | |
| 93 | #define CONFIG_SYS_FLASH_BASE 0x580000000ULL |
| 94 | #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 |
| 95 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 |
| 96 | |
| 97 | #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 |
| 98 | #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 |
| 99 | |
| 100 | #ifndef __ASSEMBLY__ |
| 101 | unsigned long long get_qixis_addr(void); |
| 102 | #endif |
| 103 | |
| 104 | #define QIXIS_BASE get_qixis_addr() |
| 105 | #define QIXIS_BASE_PHYS 0x20000000 |
| 106 | #define QIXIS_BASE_PHYS_EARLY 0xC000000 |
| 107 | |
| 108 | |
| 109 | #define CONFIG_SYS_NAND_BASE 0x530000000ULL |
| 110 | #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 |
| 111 | |
| 112 | |
| 113 | /* MC firmware */ |
| 114 | /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ |
| 115 | #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 |
| 116 | #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 |
| 117 | #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 |
| 118 | #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 |
| 119 | #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 |
| 120 | #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 |
| 121 | /* |
| 122 | * Carve out a DDR region which will not be used by u-boot/Linux |
| 123 | * |
| 124 | * It will be used by MC and Debug Server. The MC region must be |
| 125 | * 512MB aligned, so the min size to hide is 512MB. |
| 126 | */ |
| 127 | |
| 128 | #if defined(CONFIG_FSL_MC_ENET) |
| 129 | #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) |
| 130 | #endif |
| 131 | |
| 132 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| 133 | |
| 134 | /* Command line configuration */ |
| 135 | #define CONFIG_CMD_GREPENV |
| 136 | #define CONFIG_CMD_CACHE |
| 137 | |
| 138 | /* Miscellaneous configurable options */ |
| 139 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) |
| 140 | |
| 141 | /* Physical Memory Map */ |
| 142 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |
| 143 | |
| 144 | #define CONFIG_NR_DRAM_BANKS 2 |
| 145 | |
| 146 | #define CONFIG_HWCONFIG |
| 147 | #define HWCONFIG_BUFFER_SIZE 128 |
| 148 | |
| 149 | /* #define CONFIG_DISPLAY_CPUINFO */ |
| 150 | |
| 151 | /* Allow to overwrite serial and ethaddr */ |
| 152 | #define CONFIG_ENV_OVERWRITE |
| 153 | |
| 154 | /* Initial environment variables */ |
| 155 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 156 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
| 157 | "loadaddr=0x80100000\0" \ |
| 158 | "kernel_addr=0x100000\0" \ |
| 159 | "ramdisk_addr=0x800000\0" \ |
| 160 | "ramdisk_size=0x2000000\0" \ |
| 161 | "fdt_high=0xa0000000\0" \ |
| 162 | "initrd_high=0xffffffffffffffff\0" \ |
| 163 | "kernel_start=0x581000000\0" \ |
| 164 | "kernel_load=0xa0000000\0" \ |
| 165 | "kernel_size=0x2800000\0" \ |
| 166 | "console=ttyAMA0,38400n8\0" \ |
| 167 | "mcinitcmd=fsl_mc start mc 0x580a00000" \ |
| 168 | " 0x580e00000 \0" |
| 169 | |
| 170 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
| 171 | "earlycon=uart8250,mmio,0x21c0500 " \ |
| 172 | "ramdisk_size=0x3000000 default_hugepagesz=2m" \ |
| 173 | " hugepagesz=2m hugepages=256" |
| 174 | #if defined(CONFIG_QSPI_BOOT) |
| 175 | #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ |
| 176 | "sf read 0x80200000 0xd00000 0x100000;"\ |
| 177 | " fsl_mc apply dpl 0x80200000 &&" \ |
| 178 | " sf read $kernel_load $kernel_start" \ |
| 179 | " $kernel_size && bootm $kernel_load" |
| 180 | #else /* NOR BOOT*/ |
| 181 | #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ |
| 182 | " cp.b $kernel_start $kernel_load" \ |
| 183 | " $kernel_size && bootm $kernel_load" |
| 184 | #endif |
| 185 | |
| 186 | /* Monitor Command Prompt */ |
| 187 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 188 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 189 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 190 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 191 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
| 192 | #define CONFIG_SYS_LONGHELP |
| 193 | #define CONFIG_CMDLINE_EDITING 1 |
| 194 | #define CONFIG_AUTO_COMPLETE |
| 195 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 196 | |
| 197 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 198 | |
| 199 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 200 | |
| 201 | #endif /* __LS1088_COMMON_H */ |