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Phil Edworthy2b3228d2011-06-01 07:35:13 +01001/*
Phil Edworthy958b7542011-06-09 16:22:43 +01002 * Configuation settings for the Renesas RSK2+SH7264 board
Phil Edworthy2b3228d2011-06-01 07:35:13 +01003 *
4 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Phil Edworthy2b3228d2011-06-01 07:35:13 +01009 */
10
11#ifndef __RSK7264_H
12#define __RSK7264_H
13
14#undef DEBUG
Phil Edworthy2b3228d2011-06-01 07:35:13 +010015#define CONFIG_CPU_SH7264 1
Phil Edworthy958b7542011-06-09 16:22:43 +010016#define CONFIG_RSK7264 1
Phil Edworthy2b3228d2011-06-01 07:35:13 +010017
Phil Edworthy2b3228d2011-06-01 07:35:13 +010018#define CONFIG_BAUDRATE 115200
19#define CONFIG_BOOTARGS "console=ttySC3,115200"
Phil Edworthy958b7542011-06-09 16:22:43 +010020#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
Phil Edworthy2b3228d2011-06-01 07:35:13 +010021
Phil Edworthy958b7542011-06-09 16:22:43 +010022#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010023#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
24#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
25#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010026
Phil Edworthy958b7542011-06-09 16:22:43 +010027/* Serial */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010028#define CONFIG_SCIF_CONSOLE 1
29#define CONFIG_CONS_SCIF3 1
30
Phil Edworthy958b7542011-06-09 16:22:43 +010031/* Memory */
32/* u-boot relocated to top 256KB of ram */
33#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
34#define CONFIG_SYS_SDRAM_BASE 0x0C000000
Phil Edworthy2b3228d2011-06-01 07:35:13 +010035#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
36
Phil Edworthy958b7542011-06-09 16:22:43 +010037#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
38#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010039#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Phil Edworthy958b7542011-06-09 16:22:43 +010040#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
41#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010042
Phil Edworthy958b7542011-06-09 16:22:43 +010043/* Flash */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010044#define CONFIG_FLASH_CFI_DRIVER
45#define CONFIG_SYS_FLASH_CFI
46#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Phil Edworthy958b7542011-06-09 16:22:43 +010047#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010048#define CONFIG_SYS_MAX_FLASH_BANKS 1
Phil Edworthy958b7542011-06-09 16:22:43 +010049#define CONFIG_SYS_MAX_FLASH_SECT 512
Phil Edworthy2b3228d2011-06-01 07:35:13 +010050
Phil Edworthy958b7542011-06-09 16:22:43 +010051#define CONFIG_ENV_IS_IN_FLASH 1
52#define CONFIG_ENV_OFFSET (128 * 1024)
53#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010054#define CONFIG_ENV_SECT_SIZE (128 * 1024)
55#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Phil Edworthy2b3228d2011-06-01 07:35:13 +010056
57/* Board Clock */
Phil Edworthyf701b5e2012-02-13 02:03:50 +000058#define CONFIG_SYS_CLK_FREQ 36000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090059#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
60#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthy958b7542011-06-09 16:22:43 +010061#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsubefb5cc2014-01-08 14:57:30 +090062#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010063
64/* Network interface */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010065#define CONFIG_SMC911X
66#define CONFIG_SMC911X_16_BIT
Phil Edworthy958b7542011-06-09 16:22:43 +010067#define CONFIG_SMC911X_BASE 0x28000000
Phil Edworthy2b3228d2011-06-01 07:35:13 +010068
69#endif /* __RSK7264_H */