| Simon Glass | d21f34e | 2016-03-11 22:07:26 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * From Coreboot soc/intel/broadwell/include/soc/pei_data.h |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #ifndef ASM_ARCH_PEI_DATA_H |
| 10 | #define ASM_ARCH_PEI_DATA_H |
| 11 | |
| 12 | #include <linux/linkage.h> |
| 13 | |
| 14 | #define PEI_VERSION 22 |
| 15 | |
| 16 | typedef void asmlinkage (*tx_byte_func)(unsigned char byte); |
| 17 | |
| 18 | enum board_type { |
| 19 | BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */ |
| 20 | BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */ |
| 21 | BOARD_TYPE_USER1, /* SV mobile */ |
| 22 | BOARD_TYPE_USER2, /* SV desktop */ |
| 23 | BOARD_TYPE_USER3, /* SV server */ |
| 24 | BOARD_TYPE_ULT, /* ULT */ |
| 25 | BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */ |
| 26 | BOARD_TYPE_UNKNOWN, |
| 27 | }; |
| 28 | |
| 29 | #define MAX_USB2_PORTS 14 |
| 30 | #define MAX_USB3_PORTS 6 |
| 31 | #define USB_OC_PIN_SKIP 8 |
| 32 | |
| 33 | enum usb2_port_location { |
| 34 | USB_PORT_BACK_PANEL = 0, |
| 35 | USB_PORT_FRONT_PANEL, |
| 36 | USB_PORT_DOCK, |
| 37 | USB_PORT_MINI_PCIE, |
| 38 | USB_PORT_FLEX, |
| 39 | USB_PORT_INTERNAL, |
| 40 | USB_PORT_SKIP, |
| 41 | USB_PORT_NGFF_DEVICE_DOWN, |
| 42 | }; |
| 43 | |
| 44 | struct usb2_port_setting { |
| 45 | /* |
| 46 | * Usb Port Length: |
| 47 | * [16:4] = length in inches in octal format |
| 48 | * [3:0] = decimal point |
| 49 | */ |
| 50 | uint16_t length; |
| 51 | uint8_t enable; |
| 52 | uint8_t oc_pin; |
| 53 | uint8_t location; |
| 54 | } __packed; |
| 55 | |
| 56 | struct usb3_port_setting { |
| 57 | uint8_t enable; |
| 58 | uint8_t oc_pin; |
| 59 | /* |
| 60 | * Set to 0 if trace length is > 5 inches |
| 61 | * Set to 1 if trace length is <= 5 inches |
| 62 | */ |
| 63 | uint8_t fixed_eq; |
| 64 | } __packed; |
| 65 | |
| 66 | |
| 67 | struct pei_data { |
| 68 | uint32_t pei_version; |
| 69 | |
| 70 | enum board_type board_type; |
| 71 | int boot_mode; |
| 72 | int ec_present; |
| 73 | int usbdebug; |
| 74 | |
| 75 | /* Base addresses */ |
| 76 | uint32_t pciexbar; |
| 77 | uint16_t smbusbar; |
| 78 | uint32_t xhcibar; |
| 79 | uint32_t ehcibar; |
| 80 | uint32_t gttbar; |
| 81 | uint32_t rcba; |
| 82 | uint32_t pmbase; |
| 83 | uint32_t gpiobase; |
| 84 | uint32_t temp_mmio_base; |
| 85 | uint32_t tseg_size; |
| 86 | |
| 87 | /* |
| 88 | * 0 = leave channel enabled |
| 89 | * 1 = disable dimm 0 on channel |
| 90 | * 2 = disable dimm 1 on channel |
| 91 | * 3 = disable dimm 0+1 on channel |
| 92 | */ |
| 93 | int dimm_channel0_disabled; |
| 94 | int dimm_channel1_disabled; |
| 95 | /* Set to 0 for memory down */ |
| 96 | uint8_t spd_addresses[4]; |
| 97 | /* Enable 2x Refresh Mode */ |
| 98 | int ddr_refresh_2x; |
| 99 | /* DQ pins are interleaved on board */ |
| 100 | int dq_pins_interleaved; |
| 101 | /* Limit DDR3 frequency */ |
| 102 | int max_ddr3_freq; |
| 103 | /* Disable self refresh */ |
| 104 | int disable_self_refresh; |
| 105 | /* Disable cmd power/CKEPD */ |
| 106 | int disable_cmd_pwr; |
| 107 | |
| 108 | /* USB port configuration */ |
| 109 | struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; |
| 110 | struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; |
| 111 | |
| 112 | /* |
| 113 | * USB3 board specific PHY tuning |
| 114 | */ |
| 115 | |
| 116 | /* Valid range: 0x69 - 0x80 */ |
| 117 | uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS]; |
| 118 | /* Valid range: 0x80 - 0x9c */ |
| 119 | uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS]; |
| 120 | /* Valid range: 0x39 - 0x80 */ |
| 121 | uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS]; |
| 122 | /* Valid range: 0x3d - 0x4a */ |
| 123 | uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS]; |
| 124 | |
| 125 | /* Console output function */ |
| 126 | tx_byte_func tx_byte; |
| 127 | |
| 128 | /* |
| 129 | * DIMM SPD data for memory down configurations |
| 130 | * [CHANNEL][SLOT][SPD] |
| 131 | */ |
| 132 | uint8_t spd_data[2][2][512]; |
| 133 | |
| 134 | /* |
| 135 | * LPDDR3 DQ byte map |
| 136 | * [CHANNEL][ITERATION][2] |
| 137 | * |
| 138 | * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) |
| 139 | * DQByteMap[0] - ClkDQByteMap: |
| 140 | * - If clock is per rank, program to [0xFF, 0xFF] |
| 141 | * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] |
| 142 | * - If clock is shared by 2 ranks but does not go to all bytes, |
| 143 | * Entry[i] defines which DQ bytes Group i services |
| 144 | * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB |
| 145 | * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB |
| 146 | * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB |
| 147 | * For DDR, DQByteMap[3:1] = [0xFF, 0] |
| 148 | * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] |
| 149 | * since we have 1 CTL / rank |
| 150 | * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] |
| 151 | * since we have 1 CA Vref |
| 152 | */ |
| 153 | uint8_t dq_map[2][6][2]; |
| 154 | |
| 155 | /* |
| 156 | * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins |
| 157 | * [CHANNEL][MAX_BYTES] |
| 158 | */ |
| 159 | uint8_t dqs_map[2][8]; |
| 160 | |
| 161 | /* Data read from flash and passed into MRC */ |
| 162 | const void *saved_data; |
| 163 | int saved_data_size; |
| 164 | |
| 165 | /* Disable use of saved data (can be set by mainboard) */ |
| 166 | int disable_saved_data; |
| 167 | |
| 168 | /* Data from MRC that should be saved to flash */ |
| 169 | void *data_to_save; |
| 170 | int data_to_save_size; |
| 171 | struct pei_memory_info meminfo; |
| 172 | } __packed; |
| 173 | |
| 174 | void mainboard_fill_pei_data(struct pei_data *pei_data); |
| 175 | void broadwell_fill_pei_data(struct pei_data *pei_data); |
| 176 | |
| 177 | #endif |