| Marek Vasut | d1fcb36 | 2011-11-08 23:18:25 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Freescale i.MX28 USB OTG Register Definitions |
| 3 | * |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 5 | * on behalf of DENX Software Engineering GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | #ifndef __REGS_USB_H__ |
| 24 | #define __REGS_USB_H__ |
| 25 | |
| 26 | struct mx28_usb_regs { |
| 27 | uint32_t hw_usbctrl_id; /* 0x000 */ |
| 28 | uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ |
| 29 | uint32_t hw_usbctrl_hwhost; /* 0x008 */ |
| 30 | uint32_t hw_usbctrl_hwdevice; /* 0x00c */ |
| 31 | uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ |
| 32 | uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ |
| 33 | |
| 34 | uint32_t reserved1[26]; |
| 35 | |
| 36 | uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ |
| 37 | uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ |
| 38 | uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ |
| 39 | uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ |
| 40 | uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ |
| 41 | |
| 42 | uint32_t reserved2[27]; |
| 43 | |
| 44 | uint32_t hw_usbctrl_caplength; /* 0x100 */ |
| 45 | uint32_t hw_usbctrl_hcsparams; /* 0x104 */ |
| 46 | uint32_t hw_usbctrl_hccparams; /* 0x108 */ |
| 47 | |
| 48 | uint32_t reserved3[5]; |
| 49 | |
| 50 | uint32_t hw_usbctrl_dciversion; /* 0x120 */ |
| 51 | uint32_t hw_usbctrl_dccparams; /* 0x124 */ |
| 52 | |
| 53 | uint32_t reserved4[6]; |
| 54 | |
| 55 | uint32_t hw_usbctrl_usbcmd; /* 0x140 */ |
| 56 | uint32_t hw_usbctrl_usbsts; /* 0x144 */ |
| 57 | uint32_t hw_usbctrl_usbintr; /* 0x148 */ |
| 58 | uint32_t hw_usbctrl_frindex; /* 0x14c */ |
| 59 | |
| 60 | uint32_t reserved5; |
| 61 | |
| 62 | union { |
| 63 | uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ |
| 64 | uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ |
| 65 | }; |
| 66 | union { |
| 67 | uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ |
| 68 | uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ |
| 69 | }; |
| 70 | |
| 71 | uint32_t hw_usbctrl_ttctrl; /* 0x15c */ |
| 72 | uint32_t hw_usbctrl_burstsize; /* 0x160 */ |
| 73 | uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ |
| 74 | |
| 75 | uint32_t reserved6; |
| 76 | |
| 77 | uint32_t hw_usbctrl_ic_usb; /* 0x16c */ |
| 78 | uint32_t hw_usbctrl_ulpi; /* 0x170 */ |
| 79 | |
| 80 | uint32_t reserved7; |
| 81 | |
| 82 | uint32_t hw_usbctrl_endptnak; /* 0x178 */ |
| 83 | uint32_t hw_usbctrl_endptnaken; /* 0x17c */ |
| 84 | |
| 85 | uint32_t reserved8; |
| 86 | |
| 87 | uint32_t hw_usbctrl_portsc1; /* 0x184 */ |
| 88 | |
| 89 | uint32_t reserved9[7]; |
| 90 | |
| 91 | uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ |
| 92 | uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ |
| 93 | uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ |
| 94 | uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ |
| 95 | uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ |
| 96 | uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ |
| 97 | uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ |
| 98 | uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ |
| 99 | uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ |
| 100 | uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ |
| 101 | uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ |
| 102 | uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ |
| 103 | uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ |
| 104 | uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ |
| 105 | uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ |
| 106 | }; |
| 107 | |
| 108 | #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) |
| 109 | |
| 110 | #define HW_USBCTRL_ID_CIVERSION_OFFSET 29 |
| 111 | #define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) |
| 112 | #define HW_USBCTRL_ID_VERSION_OFFSET 25 |
| 113 | #define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) |
| 114 | #define HW_USBCTRL_ID_REVISION_OFFSET 21 |
| 115 | #define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) |
| 116 | #define HW_USBCTRL_ID_TAG_OFFSET 16 |
| 117 | #define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) |
| 118 | #define HW_USBCTRL_ID_NID_OFFSET 8 |
| 119 | #define HW_USBCTRL_ID_NID_MASK (0x3f << 8) |
| 120 | #define HW_USBCTRL_ID_ID_OFFSET 0 |
| 121 | #define HW_USBCTRL_ID_ID_MASK (0x3f << 0) |
| 122 | |
| 123 | #define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 |
| 124 | #define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) |
| 125 | #define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 |
| 126 | #define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) |
| 127 | #define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 |
| 128 | #define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) |
| 129 | #define HW_USBCTRL_HWGENERAL_BWT (1 << 3) |
| 130 | #define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 |
| 131 | #define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) |
| 132 | #define HW_USBCTRL_HWGENERAL_RT (1 << 0) |
| 133 | |
| 134 | #define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 |
| 135 | #define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) |
| 136 | #define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 |
| 137 | #define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) |
| 138 | #define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 |
| 139 | #define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) |
| 140 | #define HW_USBCTRL_HWHOST_HC (1 << 0) |
| 141 | |
| 142 | #define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 |
| 143 | #define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) |
| 144 | #define HW_USBCTRL_HWDEVICE_DC (1 << 0) |
| 145 | |
| 146 | #define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) |
| 147 | #define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 |
| 148 | #define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) |
| 149 | #define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 |
| 150 | #define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) |
| 151 | #define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 |
| 152 | #define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff |
| 153 | |
| 154 | #define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 |
| 155 | #define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) |
| 156 | #define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 |
| 157 | #define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff |
| 158 | |
| 159 | #define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 |
| 160 | #define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff |
| 161 | |
| 162 | #define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) |
| 163 | #define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) |
| 164 | #define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) |
| 165 | #define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 |
| 166 | #define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff |
| 167 | |
| 168 | #define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 |
| 169 | #define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 |
| 170 | #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 |
| 171 | #define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 |
| 172 | #define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 |
| 173 | #define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 |
| 174 | #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 |
| 175 | #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 |
| 176 | #define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 |
| 177 | |
| 178 | #endif /* __REGS_USB_H__ */ |