Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d1fcb360bd3210b7e5d7d12babcd2a1eb1d672a3 / . / arch / arm / include / asm / arch-mb86r0x / mb86r0x.h
blob: cb9eee546206be612fc3881bc315361d4f4ae96c [file] [log] [blame]
Matthias Weisser63c36f52010-08-09 13:31:49 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 *
4 * mb86r0x definitions
5 *
6 * Author : Carsten Schneider, mycable GmbH
7 * <cs@mycable.de>
8 *
9 * (C) Copyright 2010
10 * Matthias Weisser <weisserm@arcor.de>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef MB86R0X_H
32#define MB86R0X_H
33
34#ifndef __ASSEMBLY__
35
36/* GPIO registers */
37struct mb86r0x_gpio {
38 uint32_t gpdr0;
39 uint32_t gpdr1;
40 uint32_t gpdr2;
41 uint32_t res;
42 uint32_t gpddr0;
43 uint32_t gpddr1;
44 uint32_t gpddr2;
45};
46
47/* PWM registers */
48struct mb86r0x_pwm {
49 uint32_t bcr;
50 uint32_t tpr;
51 uint32_t pr;
52 uint32_t dr;
53 uint32_t cr;
54 uint32_t sr;
55 uint32_t ccr;
56 uint32_t ir;
57};
58
59/* The mb86r0x chip control (CCNT) register set. */
60struct mb86r0x_ccnt {
61 uint32_t ccid;
62 uint32_t csrst;
63 uint32_t pad0[2];
64 uint32_t cist;
65 uint32_t cistm;
66 uint32_t cgpio_ist;
67 uint32_t cgpio_istm;
68 uint32_t cgpio_ip;
69 uint32_t cgpio_im;
70 uint32_t caxi_bw;
71 uint32_t caxi_ps;
72 uint32_t cmux_md;
73 uint32_t cex_pin_st;
74 uint32_t cmlb;
75 uint32_t pad1[1];
76 uint32_t cusb;
77 uint32_t pad2[41];
78 uint32_t cbsc;
79 uint32_t cdcrc;
80 uint32_t cmsr0;
81 uint32_t cmsr1;
82 uint32_t pad3[2];
83};
84
85/* The mb86r0x clock reset generator */
86struct mb86r0x_crg {
87 uint32_t crpr;
88 uint32_t pad0;
89 uint32_t crwr;
90 uint32_t crsr;
91 uint32_t crda;
92 uint32_t crdb;
93 uint32_t crha;
94 uint32_t crpa;
95 uint32_t crpb;
96 uint32_t crhb;
97 uint32_t cram;
98};
99
100/* The mb86r0x timer */
101struct mb86r0x_timer {
102 uint32_t load;
103 uint32_t value;
104 uint32_t control;
105 uint32_t intclr;
106 uint32_t ris;
107 uint32_t mis;
108 uint32_t bgload;
109};
110
111/* mb86r0x gdc display controller */
112struct mb86r0x_gdc_dsp {
113 /* Display settings */
114 uint32_t dcm0;
115 uint16_t pad00;
116 uint16_t htp;
117 uint16_t hdp;
118 uint16_t hdb;
119 uint16_t hsp;
120 uint8_t hsw;
121 uint8_t vsw;
122 uint16_t pad01;
123 uint16_t vtr;
124 uint16_t vsp;
125 uint16_t vdp;
126 uint16_t wx;
127 uint16_t wy;
128 uint16_t ww;
129 uint16_t wh;
130
131 /* Layer 0 */
132 uint32_t l0m;
133 uint32_t l0oa;
134 uint32_t l0da;
135 uint16_t l0dx;
136 uint16_t l0dy;
137
138 /* Layer 1 */
139 uint32_t l1m;
140 uint32_t cbda0;
141 uint32_t cbda1;
142 uint32_t pad02;
143
144 /* Layer 2 */
145 uint32_t l2m;
146 uint32_t l2oa0;
147 uint32_t l2da0;
148 uint32_t l2oa1;
149 uint32_t l2da1;
150 uint16_t l2dx;
151 uint16_t l2dy;
152
153 /* Layer 3 */
154 uint32_t l3m;
155 uint32_t l3oa0;
156 uint32_t l3da0;
157 uint32_t l3oa1;
158 uint32_t l3da1;
159 uint16_t l3dx;
160 uint16_t l3dy;
161
162 /* Layer 4 */
163 uint32_t l4m;
164 uint32_t l4oa0;
165 uint32_t l4da0;
166 uint32_t l4oa1;
167 uint32_t l4da1;
168 uint16_t l4dx;
169 uint16_t l4dy;
170
171 /* Layer 5 */
172 uint32_t l5m;
173 uint32_t l5oa0;
174 uint32_t l5da0;
175 uint32_t l5oa1;
176 uint32_t l5da1;
177 uint16_t l5dx;
178 uint16_t l5dy;
179
180 /* Cursor */
181 uint16_t cutc;
182 uint8_t cpm;
183 uint8_t csize;
184 uint32_t cuoa0;
185 uint16_t cux0;
186 uint16_t cuy0;
187 uint32_t cuoa1;
188 uint16_t cux1;
189 uint16_t cuy1;
190
191 /* Layer blending */
192 uint32_t l0bld;
193 uint32_t pad03;
194 uint32_t l0tc;
195 uint16_t l3tc;
196 uint16_t l2tc;
197 uint32_t pad04[15];
198
199 /* Display settings */
200 uint32_t dcm1;
201 uint32_t dcm2;
202 uint32_t dcm3;
203 uint32_t pad05;
204
205 /* Layer 0 extended */
206 uint32_t l0em;
207 uint16_t l0wx;
208 uint16_t l0wy;
209 uint16_t l0ww;
210 uint16_t l0wh;
211 uint32_t pad06;
212
213 /* Layer 1 extended */
214 uint32_t l1em;
215 uint16_t l1wx;
216 uint16_t l1wy;
217 uint16_t l1ww;
218 uint16_t l1wh;
219 uint32_t pad07;
220
221 /* Layer 2 extended */
222 uint32_t l2em;
223 uint16_t l2wx;
224 uint16_t l2wy;
225 uint16_t l2ww;
226 uint16_t l2wh;
227 uint32_t pad08;
228
229 /* Layer 3 extended */
230 uint32_t l3em;
231 uint16_t l3wx;
232 uint16_t l3wy;
233 uint16_t l3ww;
234 uint16_t l3wh;
235 uint32_t pad09;
236
237 /* Layer 4 extended */
238 uint32_t l4em;
239 uint16_t l4wx;
240 uint16_t l4wy;
241 uint16_t l4ww;
242 uint16_t l4wh;
243 uint32_t pad10;
244
245 /* Layer 5 extended */
246 uint32_t l5em;
247 uint16_t l5wx;
248 uint16_t l5wy;
249 uint16_t l5ww;
250 uint16_t l5wh;
251 uint32_t pad11;
252
253 /* Multi screen control */
254 uint32_t msc;
255 uint32_t pad12[3];
256 uint32_t dls;
257 uint32_t dbgc;
258
259 /* Layer blending */
260 uint32_t l1bld;
261 uint32_t l2bld;
262 uint32_t l3bld;
263 uint32_t l4bld;
264 uint32_t l5bld;
265 uint32_t pad13;
266
267 /* Extended transparency control */
268 uint32_t l0etc;
269 uint32_t l1etc;
270 uint32_t l2etc;
271 uint32_t l3etc;
272 uint32_t l4etc;
273 uint32_t l5etc;
274 uint32_t pad14[10];
275
276 /* YUV coefficients */
277 uint32_t l1ycr0;
278 uint32_t l1ycr1;
279 uint32_t l1ycg0;
280 uint32_t l1ycg1;
281 uint32_t l1ycb0;
282 uint32_t l1ycb1;
283 uint32_t pad15[130];
284
285 /* Layer palletes */
286 uint32_t l0pal[256];
287 uint32_t l1pal[256];
288 uint32_t pad16[256];
289 uint32_t l2pal[256];
290 uint32_t l3pal[256];
291 uint32_t pad17[256];
292
293 /* PWM settings */
294 uint32_t vpwmm;
295 uint16_t vpwms;
296 uint16_t vpwme;
297 uint32_t vpwmc;
298 uint32_t pad18[253];
299};
300
301/* mb86r0x gdc capture controller */
302struct mb86r0x_gdc_cap {
303 uint32_t vcm;
304 uint32_t csc;
305 uint32_t vcs;
306 uint32_t pad01;
307
308 uint32_t cbm;
309 uint32_t cboa;
310 uint32_t cbla;
311 uint16_t cihstr;
312 uint16_t civstr;
313 uint16_t cihend;
314 uint16_t civend;
315 uint32_t pad02;
316
317 uint32_t chp;
318 uint32_t cvp;
319 uint32_t pad03[4];
320
321 uint32_t clpf;
322 uint32_t pad04;
323 uint32_t cmss;
324 uint32_t cmds;
325 uint32_t pad05[12];
326
327 uint32_t rgbhc;
328 uint32_t rgbhen;
329 uint32_t rgbven;
330 uint32_t pad06;
331 uint32_t rgbs;
332 uint32_t pad07[11];
333
334 uint32_t rgbcmy;
335 uint32_t rgbcmcb;
336 uint32_t rgbcmcr;
337 uint32_t rgbcmb;
338 uint32_t pad08[12 + 1984];
339};
340
341/* mb86r0x gdc draw */
342struct mb86r0x_gdc_draw {
343 uint32_t ys;
344 uint32_t xs;
345 uint32_t dxdy;
346 uint32_t xus;
347 uint32_t dxudy;
348 uint32_t xls;
349 uint32_t dxldy;
350 uint32_t usn;
351 uint32_t lsn;
352 uint32_t pad01[7];
353 uint32_t rs;
354 uint32_t drdx;
355 uint32_t drdy;
356 uint32_t gs;
357 uint32_t dgdx;
358 uint32_t dgdy;
359 uint32_t bs;
360 uint32_t dbdx;
361 uint32_t dbdy;
362 uint32_t pad02[7];
363 uint32_t zs;
364 uint32_t dzdx;
365 uint32_t dzdy;
366 uint32_t pad03[13];
367 uint32_t ss;
368 uint32_t dsdx;
369 uint32_t dsdy;
370 uint32_t ts;
371 uint32_t dtdx;
372 uint32_t dtdy;
373 uint32_t qs;
374 uint32_t dqdx;
375 uint32_t dqdy;
376 uint32_t pad04[23];
377 uint32_t lpn;
378 uint32_t lxs;
379 uint32_t lxde;
380 uint32_t lys;
381 uint32_t lyde;
382 uint32_t lzs;
383 uint32_t lzde;
384 uint32_t pad05[13];
385 uint32_t pxdc;
386 uint32_t pydc;
387 uint32_t pzdc;
388 uint32_t pad06[25];
389 uint32_t rxs;
390 uint32_t rys;
391 uint32_t rsizex;
392 uint32_t rsizey;
393 uint32_t pad07[12];
394 uint32_t saddr;
395 uint32_t sstride;
396 uint32_t srx;
397 uint32_t sry;
398 uint32_t daddr;
399 uint32_t dstride;
400 uint32_t drx;
401 uint32_t dry;
402 uint32_t brsizex;
403 uint32_t brsizey;
404 uint32_t tcolor;
405 uint32_t pad08[93];
406 uint32_t blpo;
407 uint32_t pad09[7];
408 uint32_t ctr;
409 uint32_t ifsr;
410 uint32_t ifcnt;
411 uint32_t sst;
412 uint32_t ds;
413 uint32_t pst;
414 uint32_t est;
415 uint32_t pad10;
416 uint32_t mdr0;
417 uint32_t mdr1;
418 uint32_t mdr2;
419 uint32_t mdr3;
420 uint32_t mdr4;
421 uint32_t pad14[2];
422 uint32_t mdr7;
423 uint32_t fbr;
424 uint32_t xres;
425 uint32_t zbr;
426 uint32_t tbr;
427 uint32_t pfbr;
428 uint32_t cxmin;
429 uint32_t cxmax;
430 uint32_t cymin;
431 uint32_t cymax;
432 uint32_t txs;
433 uint32_t tis;
434 uint32_t toa;
435 uint32_t sho;
436 uint32_t abr;
437 uint32_t pad15[2];
438 uint32_t fc;
439 uint32_t bc;
440 uint32_t alf;
441 uint32_t blp;
442 uint32_t pad16;
443 uint32_t tbc;
444 uint32_t pad11[42];
445 uint32_t lx0dc;
446 uint32_t ly0dc;
447 uint32_t lx1dc;
448 uint32_t ly1dc;
449 uint32_t pad12[12];
450 uint32_t x0dc;
451 uint32_t y0dc;
452 uint32_t x1dc;
453 uint32_t y1dc;
454 uint32_t x2dc;
455 uint32_t y2dc;
456 uint32_t pad13[666];
457};
458
459/* mb86r0x gdc geometry engine */
460struct mb86r0x_gdc_geom {
461 uint32_t gctr;
462 uint32_t pad00[15];
463 uint32_t gmdr0;
464 uint32_t gmdr1;
465 uint32_t gmdr2;
466 uint32_t pad01[237];
467 uint32_t dfifog;
468 uint32_t pad02[767];
469};
470
471/* mb86r0x gdc */
472struct mb86r0x_gdc {
473 uint32_t pad00[2];
474 uint32_t lts;
475 uint32_t pad01;
476 uint32_t lsta;
477 uint32_t pad02[3];
478 uint32_t ist;
479 uint32_t imask;
480 uint32_t pad03[6];
481 uint32_t lsa;
482 uint32_t lco;
483 uint32_t lreq;
484
485 uint32_t pad04[16*1024 - 19];
486 struct mb86r0x_gdc_dsp dsp0;
487 struct mb86r0x_gdc_dsp dsp1;
488 uint32_t pad05[4*1024 - 2];
489 uint32_t vccc;
490 uint32_t vcsr;
491 struct mb86r0x_gdc_cap cap0;
492 struct mb86r0x_gdc_cap cap1;
493 uint32_t pad06[4*1024];
494 uint32_t texture_base[16*1024];
495 struct mb86r0x_gdc_draw draw;
496 uint32_t pad07[7*1024];
497 struct mb86r0x_gdc_geom geom;
498 uint32_t pad08[7*1024];
499};
500
Matthias Weisser1a905992011-08-01 05:11:52 +0000[diff] [blame]501/* mb86r0x ddr2c */
502struct mb86r0x_ddr2c {
503 uint16_t dric;
504 uint16_t dric1;
505 uint16_t dric2;
506 uint16_t drca;
507 uint16_t drcm;
508 uint16_t drcst1;
509 uint16_t drcst2;
510 uint16_t drcr;
511 uint16_t pad00[8];
512 uint16_t drcf;
513 uint16_t pad01[7];
514 uint16_t drasr;
515 uint16_t pad02[15];
516 uint16_t drims;
517 uint16_t pad03[7];
518 uint16_t dros;
519 uint16_t pad04;
520 uint16_t dribsodt1;
521 uint16_t dribsocd;
522 uint16_t dribsocd2;
523 uint16_t pad05[3];
524 uint16_t droaba;
525 uint16_t pad06[9];
526 uint16_t drobs;
527 uint16_t pad07[5];
528 uint16_t drimr1;
529 uint16_t drimr2;
530 uint16_t drimr3;
531 uint16_t drimr4;
532 uint16_t droisr1;
533 uint16_t droisr2;
534};
535
536/* mb86r0x memc */
537struct mb86r0x_memc {
538 uint32_t mcfmode[8];
539 uint32_t mcftim[8];
540 uint32_t mcfarea[8];
541};
542
Matthias Weisser63c36f52010-08-09 13:31:49 +0200[diff] [blame]543#endif /* __ASSEMBLY__ */
544
545/*
546 * Physical Address Defines
547 */
548#define MB86R0x_DDR2_BASE 0xf3000000
549#define MB86R0x_GDC_BASE 0xf1fc0000
550#define MB86R0x_CCNT_BASE 0xfff42000
551#define MB86R0x_CAN0_BASE 0xfff54000
552#define MB86R0x_CAN1_BASE 0xfff55000
553#define MB86R0x_I2C0_BASE 0xfff56000
554#define MB86R0x_I2C1_BASE 0xfff57000
555#define MB86R0x_EHCI_BASE 0xfff80000
556#define MB86R0x_OHCI_BASE 0xfff81000
557#define MB86R0x_IRC1_BASE 0xfffb0000
558#define MB86R0x_MEMC_BASE 0xfffc0000
559#define MB86R0x_TIMER_BASE 0xfffe0000
560#define MB86R0x_UART0_BASE 0xfffe1000
561#define MB86R0x_UART1_BASE 0xfffe2000
562#define MB86R0x_IRCE_BASE 0xfffe4000
563#define MB86R0x_CRG_BASE 0xfffe7000
564#define MB86R0x_IRC0_BASE 0xfffe8000
565#define MB86R0x_GPIO_BASE 0xfffe9000
566#define MB86R0x_PWM0_BASE 0xfff41000
567#define MB86R0x_PWM1_BASE 0xfff41100
568
569#define MB86R0x_CRSR_SWRSTREQ (1 << 1)
570
571/*
572 * Timer register bits
573 */
574#define MB86R0x_TIMER_ENABLE (1 << 7)
575#define MB86R0x_TIMER_MODE_MSK (1 << 6)
576#define MB86R0x_TIMER_MODE_FR (0 << 6)
577#define MB86R0x_TIMER_MODE_PD (1 << 6)
578
579#define MB86R0x_TIMER_INT_EN (1 << 5)
580#define MB86R0x_TIMER_PRS_MSK (3 << 2)
581#define MB86R0x_TIMER_PRS_4S (1 << 2)
582#define MB86R0x_TIMER_PRS_8S (1 << 3)
583#define MB86R0x_TIMER_SIZE_32 (1 << 1)
584#define MB86R0x_TIMER_ONE_SHT (1 << 0)
585
586/*
587 * Clock reset generator bits
588 */
589#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
590#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
591#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
592#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
593#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
594#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
595#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
596#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
597#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
598#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
599#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
600#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
601#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
602#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
603/*
604 * DDR2 controller bits
605 */
606#define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
607#define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
608#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
609#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
610 MB86R0x_DDR2_DRCI_CKEN | \
611 MB86R0x_DDR2_DRCI_DRCMD)
612#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
613 MB86R0x_DDR2_DRCI_CKEN)
614#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
615#endif /* MB86R0X_H */