Simon Glass | 932bc4a | 2015-08-30 16:55:28 -0600 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 Google, Inc |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_CLOCK_H |
| 8 | #define _ASM_ARCH_CLOCK_H |
| 9 | |
| 10 | /* define pll mode */ |
| 11 | #define RKCLK_PLL_MODE_SLOW 0 |
| 12 | #define RKCLK_PLL_MODE_NORMAL 1 |
| 13 | |
| 14 | enum { |
| 15 | ROCKCHIP_SYSCON_NOC, |
| 16 | ROCKCHIP_SYSCON_GRF, |
| 17 | ROCKCHIP_SYSCON_SGRF, |
| 18 | ROCKCHIP_SYSCON_PMU, |
Kever Yang | e3eba16 | 2016-08-16 17:58:10 +0800 | [diff] [blame] | 19 | ROCKCHIP_SYSCON_PMUGRF, |
Kever Yang | 62d01dc | 2017-02-13 17:38:59 +0800 | [diff] [blame] | 20 | ROCKCHIP_SYSCON_PMUSGRF, |
| 21 | ROCKCHIP_SYSCON_CIC, |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 22 | ROCKCHIP_SYSCON_MSCH, |
Simon Glass | 932bc4a | 2015-08-30 16:55:28 -0600 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | /* Standard Rockchip clock numbers */ |
| 26 | enum rk_clk_id { |
| 27 | CLK_OSC, |
| 28 | CLK_ARM, |
| 29 | CLK_DDR, |
| 30 | CLK_CODEC, |
| 31 | CLK_GENERAL, |
| 32 | CLK_NEW, |
| 33 | |
| 34 | CLK_COUNT, |
| 35 | }; |
| 36 | |
| 37 | static inline int rk_pll_id(enum rk_clk_id clk_id) |
| 38 | { |
| 39 | return clk_id - 1; |
| 40 | } |
| 41 | |
Kever Yang | 536dea8 | 2017-11-03 15:16:12 +0800 | [diff] [blame] | 42 | struct sysreset_reg { |
| 43 | unsigned int glb_srst_fst_value; |
| 44 | unsigned int glb_srst_snd_value; |
| 45 | }; |
| 46 | |
Simon Glass | 932bc4a | 2015-08-30 16:55:28 -0600 | [diff] [blame] | 47 | /** |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 48 | * clk_get_divisor() - Calculate the required clock divisior |
| 49 | * |
| 50 | * Given an input rate and a required output_rate, calculate the Rockchip |
| 51 | * divisor needed to achieve this. |
| 52 | * |
| 53 | * @input_rate: Input clock rate in Hz |
| 54 | * @output_rate: Output clock rate in Hz |
| 55 | * @return divisor register value to use |
| 56 | */ |
| 57 | static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) |
| 58 | { |
| 59 | uint clk_div; |
| 60 | |
| 61 | clk_div = input_rate / output_rate; |
| 62 | clk_div = (clk_div + 1) & 0xfffe; |
| 63 | |
| 64 | return clk_div; |
| 65 | } |
| 66 | |
| 67 | /** |
Simon Glass | 932bc4a | 2015-08-30 16:55:28 -0600 | [diff] [blame] | 68 | * rockchip_get_cru() - get a pointer to the clock/reset unit registers |
| 69 | * |
| 70 | * @return pointer to registers, or -ve error on error |
| 71 | */ |
| 72 | void *rockchip_get_cru(void); |
| 73 | |
Kever Yang | e198053 | 2017-02-13 17:38:56 +0800 | [diff] [blame] | 74 | /** |
| 75 | * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers |
| 76 | * |
| 77 | * @return pointer to registers, or -ve error on error |
| 78 | */ |
| 79 | void *rockchip_get_pmucru(void); |
| 80 | |
Simon Glass | 94906e4 | 2016-01-21 19:45:17 -0700 | [diff] [blame] | 81 | struct rk3288_cru; |
| 82 | struct rk3288_grf; |
| 83 | |
Heiko Stübner | 1bd4a54 | 2016-07-16 00:17:16 +0200 | [diff] [blame] | 84 | void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); |
Simon Glass | 94906e4 | 2016-01-21 19:45:17 -0700 | [diff] [blame] | 85 | |
Simon Glass | 156b960 | 2016-07-17 15:23:16 -0600 | [diff] [blame] | 86 | int rockchip_get_clk(struct udevice **devp); |
| 87 | |
Elaine Zhang | 432976f | 2017-12-19 18:22:38 +0800 | [diff] [blame] | 88 | /* |
| 89 | * rockchip_reset_bind() - Bind soft reset device as child of clock device |
| 90 | * |
| 91 | * @pdev: clock udevice |
| 92 | * @reg_offset: the first offset in cru for softreset registers |
| 93 | * @reg_number: the reg numbers of softreset registers |
| 94 | * @return 0 success, or error value |
| 95 | */ |
| 96 | int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); |
| 97 | |
Simon Glass | 932bc4a | 2015-08-30 16:55:28 -0600 | [diff] [blame] | 98 | #endif |