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git01.mediatek.com / filogic / uboot / d1f89072cb15232a730d270f34424f3682e89cb0 / . / arch / arm / include / asm / arch-mx8m / clock.h
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Peng Fan88057bc2018-01-10 13:20:22 +0800[diff] [blame]1/*
2 * Copyright 2017 NXP
3 *
4 * Peng Fan <peng.fan@nxp.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _ASM_ARCH_IMX8M_CLOCK_H
10#define _ASM_ARCH_IMX8M_CLOCK_H
11
12#include <linux/bitops.h>
13
14enum pll_clocks {
15 ANATOP_ARM_PLL,
16 ANATOP_GPU_PLL,
17 ANATOP_SYSTEM_PLL1,
18 ANATOP_SYSTEM_PLL2,
19 ANATOP_SYSTEM_PLL3,
20 ANATOP_AUDIO_PLL1,
21 ANATOP_AUDIO_PLL2,
22 ANATOP_VIDEO_PLL1,
23 ANATOP_VIDEO_PLL2,
24 ANATOP_DRAM_PLL,
25};
26
27enum clk_slice_type {
28 CORE_CLOCK_SLICE,
29 BUS_CLOCK_SLICE,
30 IP_CLOCK_SLICE,
31 AHB_CLOCK_SLICE,
32 IPG_CLOCK_SLICE,
33 CORE_SEL_CLOCK_SLICE,
34 DRAM_SEL_CLOCK_SLICE,
35};
36
37enum clk_root_index {
38 MXC_ARM_CLK = 0,
39 ARM_A53_CLK_ROOT = 0,
40 ARM_M4_CLK_ROOT = 1,
41 VPU_A53_CLK_ROOT = 2,
42 GPU_CORE_CLK_ROOT = 3,
43 GPU_SHADER_CLK_ROOT = 4,
44 MAIN_AXI_CLK_ROOT = 16,
45 ENET_AXI_CLK_ROOT = 17,
46 NAND_USDHC_BUS_CLK_ROOT = 18,
47 VPU_BUS_CLK_ROOT = 19,
48 DISPLAY_AXI_CLK_ROOT = 20,
49 DISPLAY_APB_CLK_ROOT = 21,
50 DISPLAY_RTRM_CLK_ROOT = 22,
51 USB_BUS_CLK_ROOT = 23,
52 GPU_AXI_CLK_ROOT = 24,
53 GPU_AHB_CLK_ROOT = 25,
54 NOC_CLK_ROOT = 26,
55 NOC_APB_CLK_ROOT = 27,
56 AHB_CLK_ROOT = 32,
57 IPG_CLK_ROOT = 33,
58 MXC_IPG_CLK = 33,
59 AUDIO_AHB_CLK_ROOT = 34,
60 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
61 DRAM_SEL_CFG = 48,
62 CORE_SEL_CFG = 49,
63 DRAM_ALT_CLK_ROOT = 64,
64 DRAM_APB_CLK_ROOT = 65,
65 VPU_G1_CLK_ROOT = 66,
66 VPU_G2_CLK_ROOT = 67,
67 DISPLAY_DTRC_CLK_ROOT = 68,
68 DISPLAY_DC8000_CLK_ROOT = 69,
69 PCIE1_CTRL_CLK_ROOT = 70,
70 PCIE1_PHY_CLK_ROOT = 71,
71 PCIE1_AUX_CLK_ROOT = 72,
72 DC_PIXEL_CLK_ROOT = 73,
73 LCDIF_PIXEL_CLK_ROOT = 74,
74 SAI1_CLK_ROOT = 75,
75 SAI2_CLK_ROOT = 76,
76 SAI3_CLK_ROOT = 77,
77 SAI4_CLK_ROOT = 78,
78 SAI5_CLK_ROOT = 79,
79 SAI6_CLK_ROOT = 80,
80 SPDIF1_CLK_ROOT = 81,
81 SPDIF2_CLK_ROOT = 82,
82 ENET_REF_CLK_ROOT = 83,
83 ENET_TIMER_CLK_ROOT = 84,
84 ENET_PHY_REF_CLK_ROOT = 85,
85 NAND_CLK_ROOT = 86,
86 QSPI_CLK_ROOT = 87,
87 MXC_ESDHC_CLK = 88,
88 USDHC1_CLK_ROOT = 88,
89 MXC_ESDHC2_CLK = 89,
90 USDHC2_CLK_ROOT = 89,
91 I2C1_CLK_ROOT = 90,
92 MXC_I2C_CLK = 90,
93 I2C2_CLK_ROOT = 91,
94 I2C3_CLK_ROOT = 92,
95 I2C4_CLK_ROOT = 93,
96 UART1_CLK_ROOT = 94,
97 UART2_CLK_ROOT = 95,
98 UART3_CLK_ROOT = 96,
99 UART4_CLK_ROOT = 97,
100 USB_CORE_REF_CLK_ROOT = 98,
101 USB_PHY_REF_CLK_ROOT = 99,
102 GIC_CLK_ROOT = 100,
103 ECSPI1_CLK_ROOT = 101,
104 ECSPI2_CLK_ROOT = 102,
105 PWM1_CLK_ROOT = 103,
106 PWM2_CLK_ROOT = 104,
107 PWM3_CLK_ROOT = 105,
108 PWM4_CLK_ROOT = 106,
109 GPT1_CLK_ROOT = 107,
110 GPT2_CLK_ROOT = 108,
111 GPT3_CLK_ROOT = 109,
112 GPT4_CLK_ROOT = 110,
113 GPT5_CLK_ROOT = 111,
114 GPT6_CLK_ROOT = 112,
115 TRACE_CLK_ROOT = 113,
116 WDOG_CLK_ROOT = 114,
117 WRCLK_CLK_ROOT = 115,
118 IPP_DO_CLKO1 = 116,
119 IPP_DO_CLKO2 = 117,
120 MIPI_DSI_CORE_CLK_ROOT = 118,
121 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
122 MIPI_DSI_DBI_CLK_ROOT = 120,
123 OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
124 MIPI_CSI1_CORE_CLK_ROOT = 122,
125 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
126 MIPI_CSI1_ESC_CLK_ROOT = 124,
127 MIPI_CSI2_CORE_CLK_ROOT = 125,
128 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
129 MIPI_CSI2_ESC_CLK_ROOT = 127,
130 PCIE2_CTRL_CLK_ROOT = 128,
131 PCIE2_PHY_CLK_ROOT = 129,
132 PCIE2_AUX_CLK_ROOT = 130,
133 ECSPI3_CLK_ROOT = 131,
134 OLD_MIPI_DSI_ESC_RX_ROOT = 132,
135 DISPLAY_HDMI_CLK_ROOT = 133,
136 CLK_ROOT_MAX,
137};
138
139enum clk_root_src {
140 OSC_25M_CLK,
141 ARM_PLL_CLK,
142 DRAM_PLL1_CLK,
143 VIDEO_PLL2_CLK,
144 VPU_PLL_CLK,
145 GPU_PLL_CLK,
146 SYSTEM_PLL1_800M_CLK,
147 SYSTEM_PLL1_400M_CLK,
148 SYSTEM_PLL1_266M_CLK,
149 SYSTEM_PLL1_200M_CLK,
150 SYSTEM_PLL1_160M_CLK,
151 SYSTEM_PLL1_133M_CLK,
152 SYSTEM_PLL1_100M_CLK,
153 SYSTEM_PLL1_80M_CLK,
154 SYSTEM_PLL1_40M_CLK,
155 SYSTEM_PLL2_1000M_CLK,
156 SYSTEM_PLL2_500M_CLK,
157 SYSTEM_PLL2_333M_CLK,
158 SYSTEM_PLL2_250M_CLK,
159 SYSTEM_PLL2_200M_CLK,
160 SYSTEM_PLL2_166M_CLK,
161 SYSTEM_PLL2_125M_CLK,
162 SYSTEM_PLL2_100M_CLK,
163 SYSTEM_PLL2_50M_CLK,
164 SYSTEM_PLL3_CLK,
165 AUDIO_PLL1_CLK,
166 AUDIO_PLL2_CLK,
167 VIDEO_PLL_CLK,
168 OSC_32K_CLK,
169 EXT_CLK_1,
170 EXT_CLK_2,
171 EXT_CLK_3,
172 EXT_CLK_4,
173 OSC_27M_CLK,
174};
175
176/* CCGR index */
177enum clk_ccgr_index {
178 CCGR_DVFS = 0,
179 CCGR_ANAMIX = 1,
180 CCGR_CPU = 2,
181 CCGR_CSU = 4,
182 CCGR_DRAM1 = 5,
183 CCGR_DRAM2_OBSOLETE = 6,
184 CCGR_ECSPI1 = 7,
185 CCGR_ECSPI2 = 8,
186 CCGR_ECSPI3 = 9,
187 CCGR_ENET1 = 10,
188 CCGR_GPIO1 = 11,
189 CCGR_GPIO2 = 12,
190 CCGR_GPIO3 = 13,
191 CCGR_GPIO4 = 14,
192 CCGR_GPIO5 = 15,
193 CCGR_GPT1 = 16,
194 CCGR_GPT2 = 17,
195 CCGR_GPT3 = 18,
196 CCGR_GPT4 = 19,
197 CCGR_GPT5 = 20,
198 CCGR_GPT6 = 21,
199 CCGR_HS = 22,
200 CCGR_I2C1 = 23,
201 CCGR_I2C2 = 24,
202 CCGR_I2C3 = 25,
203 CCGR_I2C4 = 26,
204 CCGR_IOMUX = 27,
205 CCGR_IOMUX1 = 28,
206 CCGR_IOMUX2 = 29,
207 CCGR_IOMUX3 = 30,
208 CCGR_IOMUX4 = 31,
209 CCGR_M4 = 32,
210 CCGR_MU = 33,
211 CCGR_OCOTP = 34,
212 CCGR_OCRAM = 35,
213 CCGR_OCRAM_S = 36,
214 CCGR_PCIE = 37,
215 CCGR_PERFMON1 = 38,
216 CCGR_PERFMON2 = 39,
217 CCGR_PWM1 = 40,
218 CCGR_PWM2 = 41,
219 CCGR_PWM3 = 42,
220 CCGR_PWM4 = 43,
221 CCGR_QOS = 44,
222 CCGR_DISMIX = 45,
223 CCGR_MEGAMIX = 46,
224 CCGR_QSPI = 47,
225 CCGR_RAWNAND = 48,
226 CCGR_RDC = 49,
227 CCGR_ROM = 50,
228 CCGR_SAI1 = 51,
229 CCGR_SAI2 = 52,
230 CCGR_SAI3 = 53,
231 CCGR_SAI4 = 54,
232 CCGR_SAI5 = 55,
233 CCGR_SAI6 = 56,
234 CCGR_SCTR = 57,
235 CCGR_SDMA1 = 58,
236 CCGR_SDMA2 = 59,
237 CCGR_SEC_DEBUG = 60,
238 CCGR_SEMA1 = 61,
239 CCGR_SEMA2 = 62,
240 CCGR_SIM_DISPLAY = 63,
241 CCGR_SIM_ENET = 64,
242 CCGR_SIM_M = 65,
243 CCGR_SIM_MAIN = 66,
244 CCGR_SIM_S = 67,
245 CCGR_SIM_WAKEUP = 68,
246 CCGR_SIM_USB = 69,
247 CCGR_SIM_VPU = 70,
248 CCGR_SNVS = 71,
249 CCGR_TRACE = 72,
250 CCGR_UART1 = 73,
251 CCGR_UART2 = 74,
252 CCGR_UART3 = 75,
253 CCGR_UART4 = 76,
254 CCGR_USB_CTRL1 = 77,
255 CCGR_USB_CTRL2 = 78,
256 CCGR_USB_PHY1 = 79,
257 CCGR_USB_PHY2 = 80,
258 CCGR_USDHC1 = 81,
259 CCGR_USDHC2 = 82,
260 CCGR_WDOG1 = 83,
261 CCGR_WDOG2 = 84,
262 CCGR_WDOG3 = 85,
263 CCGR_VA53 = 86,
264 CCGR_GPU = 87,
265 CCGR_HEVC = 88,
266 CCGR_AVC = 89,
267 CCGR_VP9 = 90,
268 CCGR_HEVC_INTER = 91,
269 CCGR_GIC = 92,
270 CCGR_DISPLAY = 93,
271 CCGR_HDMI = 94,
272 CCGR_HDMI_PHY = 95,
273 CCGR_XTAL = 96,
274 CCGR_PLL = 97,
275 CCGR_TSENSOR = 98,
276 CCGR_VPU_DEC = 99,
277 CCGR_PCIE2 = 100,
278 CCGR_MIPI_CSI1 = 101,
279 CCGR_MIPI_CSI2 = 102,
280 CCGR_MAX,
281};
282
283/* src index */
284enum clk_src_index {
285 CLK_SRC_CKIL_SYNC_REQ = 0,
286 CLK_SRC_ARM_PLL_EN = 1,
287 CLK_SRC_GPU_PLL_EN = 2,
288 CLK_SRC_VPU_PLL_EN = 3,
289 CLK_SRC_DRAM_PLL_EN = 4,
290 CLK_SRC_SYSTEM_PLL1_EN = 5,
291 CLK_SRC_SYSTEM_PLL2_EN = 6,
292 CLK_SRC_SYSTEM_PLL3_EN = 7,
293 CLK_SRC_AUDIO_PLL1_EN = 8,
294 CLK_SRC_AUDIO_PLL2_EN = 9,
295 CLK_SRC_VIDEO_PLL1_EN = 10,
296 CLK_SRC_VIDEO_PLL2_EN = 11,
297 CLK_SRC_ARM_PLL = 12,
298 CLK_SRC_GPU_PLL = 13,
299 CLK_SRC_VPU_PLL = 14,
300 CLK_SRC_DRAM_PLL = 15,
301 CLK_SRC_SYSTEM_PLL1_800M = 16,
302 CLK_SRC_SYSTEM_PLL1_400M = 17,
303 CLK_SRC_SYSTEM_PLL1_266M = 18,
304 CLK_SRC_SYSTEM_PLL1_200M = 19,
305 CLK_SRC_SYSTEM_PLL1_160M = 20,
306 CLK_SRC_SYSTEM_PLL1_133M = 21,
307 CLK_SRC_SYSTEM_PLL1_100M = 22,
308 CLK_SRC_SYSTEM_PLL1_80M = 23,
309 CLK_SRC_SYSTEM_PLL1_40M = 24,
310 CLK_SRC_SYSTEM_PLL2_1000M = 25,
311 CLK_SRC_SYSTEM_PLL2_500M = 26,
312 CLK_SRC_SYSTEM_PLL2_333M = 27,
313 CLK_SRC_SYSTEM_PLL2_250M = 28,
314 CLK_SRC_SYSTEM_PLL2_200M = 29,
315 CLK_SRC_SYSTEM_PLL2_166M = 30,
316 CLK_SRC_SYSTEM_PLL2_125M = 31,
317 CLK_SRC_SYSTEM_PLL2_100M = 32,
318 CLK_SRC_SYSTEM_PLL2_50M = 33,
319 CLK_SRC_SYSTEM_PLL3 = 34,
320 CLK_SRC_AUDIO_PLL1 = 35,
321 CLK_SRC_AUDIO_PLL2 = 36,
322 CLK_SRC_VIDEO_PLL1 = 37,
323 CLK_SRC_VIDEO_PLL2 = 38,
324 CLK_SRC_OSC_25M = 39,
325 CLK_SRC_OSC_27M = 40,
326};
327
328enum root_pre_div {
329 CLK_ROOT_PRE_DIV1 = 0,
330 CLK_ROOT_PRE_DIV2,
331 CLK_ROOT_PRE_DIV3,
332 CLK_ROOT_PRE_DIV4,
333 CLK_ROOT_PRE_DIV5,
334 CLK_ROOT_PRE_DIV6,
335 CLK_ROOT_PRE_DIV7,
336 CLK_ROOT_PRE_DIV8,
337};
338
339enum root_post_div {
340 CLK_ROOT_POST_DIV1 = 0,
341 CLK_ROOT_POST_DIV2,
342 CLK_ROOT_POST_DIV3,
343 CLK_ROOT_POST_DIV4,
344 CLK_ROOT_POST_DIV5,
345 CLK_ROOT_POST_DIV6,
346 CLK_ROOT_POST_DIV7,
347 CLK_ROOT_POST_DIV8,
348 CLK_ROOT_POST_DIV9,
349 CLK_ROOT_POST_DIV10,
350 CLK_ROOT_POST_DIV11,
351 CLK_ROOT_POST_DIV12,
352 CLK_ROOT_POST_DIV13,
353 CLK_ROOT_POST_DIV14,
354 CLK_ROOT_POST_DIV15,
355 CLK_ROOT_POST_DIV16,
356 CLK_ROOT_POST_DIV17,
357 CLK_ROOT_POST_DIV18,
358 CLK_ROOT_POST_DIV19,
359 CLK_ROOT_POST_DIV20,
360 CLK_ROOT_POST_DIV21,
361 CLK_ROOT_POST_DIV22,
362 CLK_ROOT_POST_DIV23,
363 CLK_ROOT_POST_DIV24,
364 CLK_ROOT_POST_DIV25,
365 CLK_ROOT_POST_DIV26,
366 CLK_ROOT_POST_DIV27,
367 CLK_ROOT_POST_DIV28,
368 CLK_ROOT_POST_DIV29,
369 CLK_ROOT_POST_DIV30,
370 CLK_ROOT_POST_DIV31,
371 CLK_ROOT_POST_DIV32,
372 CLK_ROOT_POST_DIV33,
373 CLK_ROOT_POST_DIV34,
374 CLK_ROOT_POST_DIV35,
375 CLK_ROOT_POST_DIV36,
376 CLK_ROOT_POST_DIV37,
377 CLK_ROOT_POST_DIV38,
378 CLK_ROOT_POST_DIV39,
379 CLK_ROOT_POST_DIV40,
380 CLK_ROOT_POST_DIV41,
381 CLK_ROOT_POST_DIV42,
382 CLK_ROOT_POST_DIV43,
383 CLK_ROOT_POST_DIV44,
384 CLK_ROOT_POST_DIV45,
385 CLK_ROOT_POST_DIV46,
386 CLK_ROOT_POST_DIV47,
387 CLK_ROOT_POST_DIV48,
388 CLK_ROOT_POST_DIV49,
389 CLK_ROOT_POST_DIV50,
390 CLK_ROOT_POST_DIV51,
391 CLK_ROOT_POST_DIV52,
392 CLK_ROOT_POST_DIV53,
393 CLK_ROOT_POST_DIV54,
394 CLK_ROOT_POST_DIV55,
395 CLK_ROOT_POST_DIV56,
396 CLK_ROOT_POST_DIV57,
397 CLK_ROOT_POST_DIV58,
398 CLK_ROOT_POST_DIV59,
399 CLK_ROOT_POST_DIV60,
400 CLK_ROOT_POST_DIV61,
401 CLK_ROOT_POST_DIV62,
402 CLK_ROOT_POST_DIV63,
403 CLK_ROOT_POST_DIV64,
404};
405
406struct clk_root_map {
407 enum clk_root_index entry;
408 enum clk_slice_type slice_type;
409 u32 slice_index;
410 u8 src_mux[8];
411};
412
413struct ccm_ccgr {
414 u32 ccgr;
415 u32 ccgr_set;
416 u32 ccgr_clr;
417 u32 ccgr_tog;
418};
419
420struct ccm_root {
421 u32 target_root;
422 u32 target_root_set;
423 u32 target_root_clr;
424 u32 target_root_tog;
425 u32 misc;
426 u32 misc_set;
427 u32 misc_clr;
428 u32 misc_tog;
429 u32 nm_post;
430 u32 nm_post_root_set;
431 u32 nm_post_root_clr;
432 u32 nm_post_root_tog;
433 u32 nm_pre;
434 u32 nm_pre_root_set;
435 u32 nm_pre_root_clr;
436 u32 nm_pre_root_tog;
437 u32 db_post;
438 u32 db_post_root_set;
439 u32 db_post_root_clr;
440 u32 db_post_root_tog;
441 u32 db_pre;
442 u32 db_pre_root_set;
443 u32 db_pre_root_clr;
444 u32 db_pre_root_tog;
445 u32 reserved[4];
446 u32 access_ctrl;
447 u32 access_ctrl_root_set;
448 u32 access_ctrl_root_clr;
449 u32 access_ctrl_root_tog;
450};
451
452struct ccm_reg {
453 u32 reserved_0[4096];
454 struct ccm_ccgr ccgr_array[192];
455 u32 reserved_1[3328];
456 struct ccm_root core_root[5];
457 u32 reserved_2[352];
458 struct ccm_root bus_root[12];
459 u32 reserved_3[128];
460 struct ccm_root ahb_ipg_root[4];
461 u32 reserved_4[384];
462 struct ccm_root dram_sel;
463 struct ccm_root core_sel;
464 u32 reserved_5[448];
465 struct ccm_root ip_root[78];
466};
467
468#define CCGR_CLK_ON_MASK 0x03
469#define CLK_SRC_ON_MASK 0x03
470
471#define CLK_ROOT_ON BIT(28)
472#define CLK_ROOT_OFF (0 << 28)
473#define CLK_ROOT_ENABLE_MASK BIT(28)
474#define CLK_ROOT_ENABLE_SHIFT 28
475#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
476
477/* For SEL, only use 1 bit */
478#define CLK_ROOT_SRC_MUX_MASK 0x07000000
479#define CLK_ROOT_SRC_MUX_SHIFT 24
480#define CLK_ROOT_SRC_0 0x00000000
481#define CLK_ROOT_SRC_1 0x01000000
482#define CLK_ROOT_SRC_2 0x02000000
483#define CLK_ROOT_SRC_3 0x03000000
484#define CLK_ROOT_SRC_4 0x04000000
485#define CLK_ROOT_SRC_5 0x05000000
486#define CLK_ROOT_SRC_6 0x06000000
487#define CLK_ROOT_SRC_7 0x07000000
488
489#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
490#define CLK_ROOT_PRE_DIV_SHIFT 16
491#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
492
493#define CLK_ROOT_AUDO_SLOW_EN 0x1000
494
495#define CLK_ROOT_AUDO_DIV_MASK 0x700
496#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
497#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
498
499/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
500#define CLK_ROOT_POST_DIV_MASK 0x3f
501#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
502#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
503#define CLK_ROOT_POST_DIV_SHIFT 0
504#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
505
506/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
507#define FRAC_PLL_LOCK_MASK BIT(31)
508#define FRAC_PLL_CLKE_MASK BIT(21)
509#define FRAC_PLL_PD_MASK BIT(19)
510#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
511#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
512#define FRAC_PLL_BYPASS_MASK BIT(14)
513#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
514#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
515#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
516#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
517#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
518#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
519#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
520#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
521
522#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
523#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
524#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
525#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
526
527#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
528#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
529#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
530#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
531
532/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
533#define SSCG_PLL_LOCK_MASK BIT(31)
534#define SSCG_PLL_CLKE_MASK BIT(25)
535#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
536#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
537#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
538#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
539#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
540#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
541#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
542#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
543#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
544#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
545#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
546#define SSCG_PLL_PD_MASK BIT(7)
547#define SSCG_PLL_BYPASS1_MASK BIT(5)
548#define SSCG_PLL_BYPASS2_MASK BIT(4)
549#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
550#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
551#define SSCG_PLL_REFCLK_SEL_MASK 0x3
552#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
553#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
554#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
555#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
556
557#define SSCG_PLL_SSDS_MASK BIT(8)
558#define SSCG_PLL_SSMD_MASK (0x7 << 5)
559#define SSCG_PLL_SSMF_MASK (0xf << 1)
560#define SSCG_PLL_SSE_MASK 0x1
561
562#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
563#define SSCG_PLL_REF_DIVR1_SHIFT 25
564#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
565#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
566#define SSCG_PLL_REF_DIVR2_SHIFT 19
567#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
568#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
569#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
570#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
571 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
572#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
573#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
574#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
575 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
576#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
577#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
578#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
579 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
580#define SSCG_PLL_FILTER_RANGE_MASK 0x1
581
582#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
583#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
584#define HW_DIGPROG_MINOR_MASK 0xff
585
586#define HW_OSC_27M_CLKE_MASK BIT(4)
587#define HW_OSC_25M_CLKE_MASK BIT(2)
588#define HW_OSC_32K_SEL_MASK 0x1
589#define HW_OSC_32K_SEL_RTC 0x1
590#define HW_OSC_32K_SEL_25M_DIV800 0x0
591
592#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
593#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
594#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
595#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
596#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
597#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
598#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
599#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
600#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
601#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
602#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
603#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
604
605#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
606#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
607#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
608#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
609#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
610#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
611#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
612#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
613#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
614#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
615
616#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
617#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
618#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
619#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
620#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
621#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
622#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
623
624enum enet_freq {
625 ENET_25MHZ = 0,
626 ENET_50MHZ,
627 ENET_125MHZ,
628};
629
630enum frac_pll_out_val {
631 FRAC_PLL_OUT_1000M,
632 FRAC_PLL_OUT_1600M,
633};
634
635u32 imx_get_fecclk(void);
636u32 imx_get_uartclk(void);
637int clock_init(void);
638void init_clk_usdhc(u32 index);
639void init_uart_clk(u32 index);
640void init_wdog_clk(void);
641unsigned int mxc_get_clock(enum clk_root_index clk);
642int clock_enable(enum clk_ccgr_index index, bool enable);
643int clock_root_enabled(enum clk_root_index clock_id);
644int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
645 enum root_post_div post_div, enum clk_root_src clock_src);
646int clock_set_target_val(enum clk_root_index clock_id, u32 val);
647int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
648int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
649int clock_get_postdiv(enum clk_root_index clock_id,
650 enum root_post_div *post_div);
651int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
652void mxs_set_lcdclk(u32 base_addr, u32 freq);
653int set_clk_qspi(void);
654void enable_ocotp_clk(unsigned char enable);
655int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
656int set_clk_enet(enum enet_freq type);
657#endif