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git01.mediatek.com / filogic / uboot / d1eb93bad135f615cc3750f351b613e458c37c67 / . / arch / arm / include / asm / arch-sunxi / dram_sun9i.h
blob: 41df5fe5b6f904d3d35446f14c01049b23377ea6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800[diff] [blame]2/*
3 * Sun8i platform dram controller register and constant defines
4 *
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
6 * Jerry Wang <wangflord@allwinnertech.com>
7 * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
8 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800[diff] [blame]9 */
10
11#ifndef _SUNXI_DRAM_SUN9I_H
12#define _SUNXI_DRAM_SUN9I_H
13
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#ifndef __ASSEMBLY__
15#include <linux/bitops.h>
16#endif
17
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800[diff] [blame]18struct sunxi_mctl_com_reg {
19 u32 cr; /* 0x00 */
20 u32 ccr; /* 0x04 controller configuration register */
21 u32 dbgcr; /* 0x08 */
22 u32 dbgcr1; /* 0x0c */
23 u32 rmcr; /* 0x10 */
24 u8 res1[0x1c]; /* 0x14 */
25 u32 mmcr; /* 0x30 */
26 u8 res2[0x3c]; /* 0x34 */
27 u32 mbagcr; /* 0x70 */
28 u32 mbacr; /* 0x74 */
29 u8 res3[0x10]; /* 0x78 */
30 u32 maer; /* 0x88 */
31 u8 res4[0x74]; /* 0x8c */
32 u32 mdfscr; /* 0x100 */
33 u32 mdfsmer; /* 0x104 */
34 u32 mdfsmrmr; /* 0x108 */
35 u32 mdfstr[4]; /* 0x10c */
36 u32 mdfsgcr; /* 0x11c */
37 u8 res5[0x1c]; /* 0x120 */
38 u32 mdfsivr; /* 0x13c */
39 u8 res6[0xc]; /* 0x140 */
40 u32 mdfstcr; /* 0x14c */
41};
42
43
44struct sunxi_mctl_ctl_reg {
45 u32 mstr; /* 0x00 master register */
46 u32 stat; /* 0x04 operating mode status register */
47 u8 res1[0x8]; /* 0x08 */
48 u32 mrctrl[2]; /* 0x10 mode register read/write control reg */
49 u32 mstat; /* 0x18 mode register read/write status reg */
50 u8 res2[0x4]; /* 0x1c */
51 u32 derateen; /* 0x20 temperature derate enable register */
52 u32 derateint; /* 0x24 temperature derate interval register */
53 u8 res3[0x8]; /* 0x28 */
54 u32 pwrctl; /* 0x30 low power control register */
55 u32 pwrtmg; /* 0x34 low power timing register */
56 u8 res4[0x18]; /* 0x38 */
57 u32 rfshctl0; /* 0x50 refresh control register 0 */
58 u32 rfshctl1; /* 0x54 refresh control register 1 */
59 u8 res5[0x8]; /* 0x58 */
60 u32 rfshctl3; /* 0x60 refresh control register 3 */
61 u32 rfshtmg; /* 0x64 refresh timing register */
62 u8 res6[0x68]; /* 0x68 */
63 u32 init[6]; /* 0xd0 SDRAM initialisation register */
64 u8 res7[0xc]; /* 0xe8 */
65 u32 rankctl; /* 0xf4 rank control register */
66 u8 res8[0x8]; /* 0xf8 */
67 u32 dramtmg[9]; /* 0x100 DRAM timing register */
68 u8 res9[0x5c]; /* 0x124 */
69 u32 zqctrl[3]; /* 0x180 ZQ control register */
70 u32 zqstat; /* 0x18c ZQ status register */
71 u32 dfitmg[2]; /* 0x190 DFI timing register */
72 u32 dfilpcfg; /* 0x198 DFI low power configuration register */
73 u8 res10[0x4]; /* 0x19c */
74 u32 dfiupd[4]; /* 0x1a0 DFI update register */
75 u32 dfimisc; /* 0x1b0 DFI miscellaneous control register */
76 u8 res11[0x1c]; /* 0x1b4 */
77 u32 trainctl[3]; /* 0x1d0 */
78 u32 trainstat; /* 0x1dc */
79 u8 res12[0x20]; /* 0x1e0 */
80 u32 addrmap[7]; /* 0x200 address map register */
81 u8 res13[0x24]; /* 0x21c */
82 u32 odtcfg; /* 0x240 ODT configuration register */
83 u32 odtmap; /* 0x244 ODT/rank map register */
84 u8 res14[0x8]; /* 0x248 */
85 u32 sched; /* 0x250 scheduler control register */
86 u8 res15[0x4]; /* 0x254 */
87 u32 perfhpr0; /* 0x258 high priority read CAM register 0 */
88 u32 perfhpr1; /* 0x25c high priority read CAM register 1 */
89 u32 perflpr0; /* 0x260 low priority read CAM register 0 */
90 u32 perflpr1; /* 0x264 low priority read CAM register 1 */
91 u32 perfwr0; /* 0x268 write CAM register 0 */
92 u32 perfwr1; /* 0x26c write CAM register 1 */
93};
94
95
96struct sunxi_mctl_phy_reg {
97 u8 res0[0x04]; /* 0x00 revision id ??? */
98 u32 pir; /* 0x04 PHY initialisation register */
99 u32 pgcr[4]; /* 0x08 PHY general configuration register */
100 u32 pgsr[2]; /* 0x18 PHY general status register */
101 u32 pllcr; /* 0x20 PLL control register */
102 u32 ptr[5]; /* 0x24 PHY timing register */
103 u32 acmdlr; /* 0x38 AC master delay line register */
104 u32 aclcdlr; /* 0x3c AC local calibrated delay line reg */
105 u32 acbdlr[10]; /* 0x40 AC bit delay line register */
106 u32 aciocr[6]; /* 0x68 AC IO configuration register */
107 u32 dxccr; /* 0x80 DATX8 common configuration register */
108 u32 dsgcr; /* 0x84 DRAM system general config register */
109 u32 dcr; /* 0x88 DRAM configuration register */
110 u32 dtpr[4]; /* 0x8c DRAM timing parameters register */
111 u32 mr0; /* 0x9c mode register 0 */
112 u32 mr1; /* 0xa0 mode register 1 */
113 u32 mr2; /* 0xa4 mode register 2 */
114 u32 mr3; /* 0xa8 mode register 3 */
115 u32 odtcr; /* 0xac ODT configuration register */
116 u32 dtcr; /* 0xb0 data training configuration register */
117 u32 dtar[4]; /* 0xb4 data training address register */
118 u32 dtdr[2]; /* 0xc4 data training data register */
119 u32 dtedr[2]; /* 0xcc data training eye data register */
120 u32 rdimmgcr[2]; /* 0xd4 RDIMM general configuration register */
121 u32 rdimmcr[2]; /* 0xdc RDIMM control register */
122 u32 gpr[2]; /* 0xe4 general purpose register */
123 u32 catr[2]; /* 0xec CA training register */
124 u32 dqdsr; /* 0xf4 DQS drift register */
125 u8 res1[0xc8]; /* 0xf8 */
126 u32 bistrr; /* 0x1c0 BIST run register */
127 u32 bistwcr; /* 0x1c4 BIST word count register */
128 u32 bistmskr[3]; /* 0x1c8 BIST mask register */
129 u32 bistlsr; /* 0x1d4 BIST LFSR seed register */
130 u32 bistar[3]; /* 0x1d8 BIST address register */
131 u32 bistupdr; /* 0x1e4 BIST user pattern data register */
132 u32 bistgsr; /* 0x1e8 BIST general status register */
133 u32 bistwer; /* 0x1dc BIST word error register */
134 u32 bistber[4]; /* 0x1f0 BIST bit error register */
135 u32 bistwcsr; /* 0x200 BIST word count status register */
136 u32 bistfwr[3]; /* 0x204 BIST fail word register */
137 u8 res2[0x28]; /* 0x210 */
138 u32 iovcr[2]; /* 0x238 IO VREF control register */
139 struct ddrphy_zq {
140 u32 cr; /* impedance control register */
141 u32 pr; /* impedance control data register */
142 u32 dr; /* impedance control data register */
143 u32 sr; /* impedance control status register */
144 } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */
145 struct ddrphy_dx {
146 u32 gcr[4]; /* DATX8 general configuration register */
147 u32 gsr[3]; /* DATX8 general status register */
148 u32 bdlr[7]; /* DATX8 bit delay line register */
149 u32 lcdlr[3]; /* DATX8 local calibrated delay line reg */
150 u32 mdlr; /* DATX8 master delay line register */
151 u32 gtr; /* DATX8 general timing register */
152 u8 res[0x34];
153 } dx[4]; /* 0x280, 0x300, 0x380, 0x400 */
154};
155
156/*
157 * DRAM common (sunxi_mctl_com_reg) register constants.
158 */
159#define MCTL_CR_RANK_MASK (3 << 0)
160#define MCTL_CR_RANK(x) (((x) - 1) << 0)
161#define MCTL_CR_BANK_MASK (3 << 2)
162#define MCTL_CR_BANK(x) ((x) << 2)
163#define MCTL_CR_ROW_MASK (0xf << 4)
164#define MCTL_CR_ROW(x) (((x) - 1) << 4)
165#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
166#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
167#define MCTL_CR_BUSW_MASK (3 << 12)
168#define MCTL_CR_BUSW16 (1 << 12)
169#define MCTL_CR_BUSW32 (3 << 12)
170#define MCTL_CR_DRAMTYPE_MASK (7 << 16)
171#define MCTL_CR_DRAMTYPE_DDR2 (2 << 16)
172#define MCTL_CR_DRAMTYPE_DDR3 (3 << 16)
173#define MCTL_CR_DRAMTYPE_LPDDR2 (6 << 16)
174
175#define MCTL_CR_CHANNEL_MASK ((1 << 22) | (1 << 20) | (1 << 19))
176#define MCTL_CR_CHANNEL_SINGLE (1 << 22)
177#define MCTL_CR_CHANNEL_DUAL ((1 << 22) | (1 << 20) | (1 << 19))
178
179#define MCTL_CCR_CH0_CLK_EN (1 << 15)
180#define MCTL_CCR_CH1_CLK_EN (1 << 31)
181
182/*
183 * post_cke_x1024 [bits 16..25]: Cycles to wait after driving CKE high
184 * to start the SDRAM initialization sequence (in 1024s of cycles).
185 */
186#define MCTL_INIT0_POST_CKE_x1024(n) ((n & 0x0fff) << 16)
187/*
188 * pre_cke_x1024 [bits 0..11] Cycles to wait after reset before driving
189 * CKE high to start the SDRAM initialization (in 1024s of cycles)
190 */
191#define MCTL_INIT0_PRE_CKE_x1024(n) ((n & 0x0fff) << 0)
192#define MCTL_INIT1_DRAM_RSTN_x1024(n) ((n & 0xff) << 16)
193#define MCTL_INIT1_FINAL_WAIT_x32(n) ((n & 0x3f) << 8)
194#define MCTL_INIT1_PRE_OCD_x32(n) ((n & 0x0f) << 0)
195#define MCTL_INIT2_IDLE_AFTER_RESET_x32(n) ((n & 0xff) << 8)
196#define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n) ((n & 0x0f) << 0)
197#define MCTL_INIT3_MR(n) ((n & 0xffff) << 16)
198#define MCTL_INIT3_EMR(n) ((n & 0xffff) << 0)
199#define MCTL_INIT4_EMR2(n) ((n & 0xffff) << 16)
200#define MCTL_INIT4_EMR3(n) ((n & 0xffff) << 0)
201#define MCTL_INIT5_DEV_ZQINIT_x32(n) ((n & 0x00ff) << 16)
202#define MCTL_INIT5_MAX_AUTO_INIT_x1024(n) ((n & 0x03ff) << 0);
203
204#define MCTL_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0)
205#define MCTL_DFIUPD0_DIS_AUTO_CTRLUPD (1 << 31)
206
207#define MCTL_MSTR_DEVICETYPE_DDR3 1
208#define MCTL_MSTR_DEVICETYPE_LPDDR2 4
209#define MCTL_MSTR_DEVICETYPE_LPDDR3 8
210#define MCTL_MSTR_DEVICETYPE(type) \
211 ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \
212 ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_DEVICETYPE_LPDDR2 : \
213 MCTL_MSTR_DEVICETYPE_LPDDR3))
214#define MCTL_MSTR_BURSTLENGTH4 (2 << 16)
215#define MCTL_MSTR_BURSTLENGTH8 (4 << 16)
216#define MCTL_MSTR_BURSTLENGTH16 (8 << 16)
217#define MCTL_MSTR_BURSTLENGTH(type) \
218 ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \
219 ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_BURSTLENGTH4 : \
220 MCTL_MSTR_BURSTLENGTH8))
221#define MCTL_MSTR_ACTIVERANKS(x) (((x == 2) ? 3 : 1) << 24)
222#define MCTL_MSTR_BUSWIDTH8 (2 << 12)
223#define MCTL_MSTR_BUSWIDTH16 (1 << 12)
224#define MCTL_MSTR_BUSWIDTH32 (0 << 12)
225#define MCTL_MSTR_2TMODE (1 << 10)
226
227#define MCTL_RFSHCTL3_DIS_AUTO_REFRESH (1 << 0)
228
229#define MCTL_ZQCTRL0_TZQCS(x) (x << 0)
230#define MCTL_ZQCTRL0_TZQCL(x) (x << 16)
231#define MCTL_ZQCTRL0_ZQCL_DIS (1 << 30)
232#define MCTL_ZQCTRL0_ZQCS_DIS (1 << 31)
233#define MCTL_ZQCTRL1_TZQRESET(x) (x << 20)
234#define MCTL_ZQCTRL1_TZQSI_x1024(x) (x << 0)
235#define MCTL_ZQCTRL2_TZRESET_TRIGGER (1 << 0)
236
237#define MCTL_PHY_DCR_BYTEMASK (1 << 10)
238#define MCTL_PHY_DCR_2TMODE (1 << 28)
239#define MCTL_PHY_DCR_DDR8BNK (1 << 3)
240#define MCTL_PHY_DRAMMODE_DDR3 3
241#define MCTL_PHY_DRAMMODE_LPDDR2 0
242#define MCTL_PHY_DRAMMODE_LPDDR3 1
243
244#define MCTL_DTCR_DEFAULT 0x00003007
245#define MCTL_DTCR_RANKEN(n) (((n == 2) ? 3 : 1) << 24)
246
247#define MCTL_PGCR1_ZCKSEL_MASK (3 << 23)
248#define MCTL_PGCR1_IODDRM_MASK (3 << 7)
249#define MCTL_PGCR1_IODDRM_DDR3 (1 << 7)
250#define MCTL_PGCR1_IODDRM_DDR3L (2 << 7)
251#define MCTL_PGCR1_INHVT_EN (1 << 26)
252
253#define MCTL_PLLGCR_PLL_BYPASS (1 << 31)
254#define MCTL_PLLGCR_PLL_POWERDOWN (1 << 29)
255
256#define MCTL_PIR_PLL_BYPASS (1 << 17)
257#define MCTL_PIR_MASK (~(1 << 17))
258#define MCTL_PIR_INIT (1 << 0)
259
260#define MCTL_PGSR0_ERRORS (0x1ff << 20)
261
262/* Constants for assembling MR0 */
263#define DDR3_MR0_PPD_FAST_EXIT (1 << 12)
264#define DDR3_MR0_WR(n) \
265 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
266#define DDR3_MR0_CL(n) \
267 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
268#define DDR3_MR0_BL8 (0 << 0)
269
270#define DDR3_MR1_RTT120OHM ((0 << 9) | (1 << 6) | (0 << 2))
271
272#define DDR3_MR2_TWL(n) \
273 (((n - 5) & 0x7) << 3)
274
275#define MCTL_NS2CYCLES_CEIL(ns) ((ns * (CONFIG_DRAM_CLK / 2) + 999) / 1000)
276
277#define DRAM_TYPE_DDR3 3
278#define DRAM_TYPE_LPDDR2 6
279#define DRAM_TYPE_LPDDR3 7
280
281#endif