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Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
Gong Qianyu5e847792015-11-11 17:58:36 +08002/*
Wasim Khan05ee3882020-09-28 16:26:11 +05303 * Device Tree Include file for NXP Layerscape-1043A family SoC.
Gong Qianyu5e847792015-11-11 17:58:36 +08004 *
Wasim Khan05ee3882020-09-28 16:26:11 +05305 * Copyright 2020 NXP
Gong Qianyu5e847792015-11-11 17:58:36 +08006 * Copyright (C) 2014-2015, Freescale Semiconductor
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
Gong Qianyu5e847792015-11-11 17:58:36 +08009 */
10
11/include/ "skeleton64.dtsi"
12
13/ {
14 compatible = "fsl,ls1043a";
15 interrupt-parent = <&gic>;
Gong Qianyu5e847792015-11-11 17:58:36 +080016
17 sysclk: sysclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <100000000>;
21 clock-output-names = "sysclk";
22 };
23
24 gic: interrupt-controller@1400000 {
25 compatible = "arm,gic-400";
26 #interrupt-cells = <3>;
27 interrupt-controller;
28 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
29 <0x0 0x1402000 0 0x2000>, /* GICC */
30 <0x0 0x1404000 0 0x2000>, /* GICH */
31 <0x0 0x1406000 0 0x2000>; /* GICV */
32 interrupts = <1 9 0xf08>;
33 };
34
Madalin Bucurd0d3e5e2020-04-23 16:25:13 +030035 soc: soc {
Gong Qianyu5e847792015-11-11 17:58:36 +080036 compatible = "simple-bus";
37 #address-cells = <2>;
38 #size-cells = <2>;
39 ranges;
40
41 clockgen: clocking@1ee1000 {
42 compatible = "fsl,ls1043a-clockgen";
43 reg = <0x0 0x1ee1000 0x0 0x1000>;
44 #clock-cells = <2>;
45 clocks = <&sysclk>;
46 };
47
Gong Qianyu8a43f132015-11-11 17:58:39 +080048 dspi0: dspi@2100000 {
49 compatible = "fsl,vf610-dspi";
50 #address-cells = <1>;
51 #size-cells = <0>;
52 reg = <0x0 0x2100000 0x0 0x10000>;
53 interrupts = <0 64 0x4>;
54 clock-names = "dspi";
55 clocks = <&clockgen 4 0>;
56 num-cs = <6>;
57 big-endian;
58 status = "disabled";
59 };
60
61 dspi1: dspi@2110000 {
62 compatible = "fsl,vf610-dspi";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 reg = <0x0 0x2110000 0x0 0x10000>;
66 interrupts = <0 65 0x4>;
67 clock-names = "dspi";
68 clocks = <&clockgen 4 0>;
69 num-cs = <6>;
70 big-endian;
71 status = "disabled";
72 };
73
Yinbo Zhuc106af62018-09-25 14:47:10 +080074 esdhc: esdhc@1560000 {
75 compatible = "fsl,esdhc";
76 reg = <0x0 0x1560000 0x0 0x10000>;
77 interrupts = <0 62 0x4>;
78 big-endian;
79 bus-width = <4>;
80 };
81
Gong Qianyu5e847792015-11-11 17:58:36 +080082 ifc: ifc@1530000 {
83 compatible = "fsl,ifc", "simple-bus";
84 reg = <0x0 0x1530000 0x0 0x10000>;
85 interrupts = <0 43 0x4>;
86 };
87
88 i2c0: i2c@2180000 {
89 compatible = "fsl,vf610-i2c";
90 #address-cells = <1>;
91 #size-cells = <0>;
92 reg = <0x0 0x2180000 0x0 0x10000>;
93 interrupts = <0 56 0x4>;
94 clock-names = "i2c";
95 clocks = <&clockgen 4 0>;
96 status = "disabled";
97 };
98
99 i2c1: i2c@2190000 {
100 compatible = "fsl,vf610-i2c";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 reg = <0x0 0x2190000 0x0 0x10000>;
104 interrupts = <0 57 0x4>;
105 clock-names = "i2c";
106 clocks = <&clockgen 4 0>;
107 status = "disabled";
108 };
109
110 i2c2: i2c@21a0000 {
111 compatible = "fsl,vf610-i2c";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0x0 0x21a0000 0x0 0x10000>;
115 interrupts = <0 58 0x4>;
116 clock-names = "i2c";
117 clocks = <&clockgen 4 0>;
118 status = "disabled";
119 };
120
121 i2c3: i2c@21b0000 {
122 compatible = "fsl,vf610-i2c";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <0x0 0x21b0000 0x0 0x10000>;
126 interrupts = <0 59 0x4>;
127 clock-names = "i2c";
128 clocks = <&clockgen 4 0>;
129 status = "disabled";
130 };
131
132 duart0: serial@21c0500 {
133 compatible = "fsl,ns16550", "ns16550a";
134 reg = <0x00 0x21c0500 0x0 0x100>;
135 interrupts = <0 54 0x4>;
136 clocks = <&clockgen 4 0>;
137 };
138
139 duart1: serial@21c0600 {
140 compatible = "fsl,ns16550", "ns16550a";
141 reg = <0x00 0x21c0600 0x0 0x100>;
142 interrupts = <0 54 0x4>;
143 clocks = <&clockgen 4 0>;
144 };
145
146 duart2: serial@21d0500 {
147 compatible = "fsl,ns16550", "ns16550a";
148 reg = <0x0 0x21d0500 0x0 0x100>;
149 interrupts = <0 55 0x4>;
150 clocks = <&clockgen 4 0>;
151 };
152
153 duart3: serial@21d0600 {
154 compatible = "fsl,ns16550", "ns16550a";
155 reg = <0x0 0x21d0600 0x0 0x100>;
156 interrupts = <0 55 0x4>;
157 clocks = <&clockgen 4 0>;
158 };
Wenbin Song7e6b49e2016-01-21 17:14:55 +0800159
160 lpuart0: serial@2950000 {
161 compatible = "fsl,ls1021a-lpuart";
162 reg = <0x0 0x2950000 0x0 0x1000>;
163 interrupts = <0 48 0x4>;
164 clocks = <&sysclk>;
165 clock-names = "ipg";
166 status = "disabled";
167 };
168
169 lpuart1: serial@2960000 {
170 compatible = "fsl,ls1021a-lpuart";
171 reg = <0x0 0x2960000 0x0 0x1000>;
172 interrupts = <0 49 0x4>;
173 clocks = <&sysclk>;
174 clock-names = "ipg";
175 status = "disabled";
176 };
177
178 lpuart2: serial@2970000 {
179 compatible = "fsl,ls1021a-lpuart";
180 reg = <0x0 0x2970000 0x0 0x1000>;
181 interrupts = <0 50 0x4>;
182 clock-names = "ipg";
183 clocks = <&sysclk>;
184 status = "disabled";
185 };
186
187 lpuart3: serial@2980000 {
188 compatible = "fsl,ls1021a-lpuart";
189 reg = <0x0 0x2980000 0x0 0x1000>;
190 interrupts = <0 51 0x4>;
191 clocks = <&sysclk>;
192 clock-names = "ipg";
193 status = "disabled";
194 };
195
196 lpuart4: serial@2990000 {
197 compatible = "fsl,ls1021a-lpuart";
198 reg = <0x0 0x2990000 0x0 0x1000>;
199 interrupts = <0 52 0x4>;
200 clocks = <&sysclk>;
201 clock-names = "ipg";
202 status = "disabled";
203 };
204
205 lpuart5: serial@29a0000 {
206 compatible = "fsl,ls1021a-lpuart";
207 reg = <0x0 0x29a0000 0x0 0x1000>;
208 interrupts = <0 53 0x4>;
209 clocks = <&sysclk>;
210 clock-names = "ipg";
211 status = "disabled";
212 };
Gong Qianyu760df892016-01-25 15:16:06 +0800213 qspi: quadspi@1550000 {
Kuldeep Singh4c380872019-12-12 11:49:24 +0530214 compatible = "fsl,ls1021a-qspi";
Gong Qianyu760df892016-01-25 15:16:06 +0800215 #address-cells = <1>;
216 #size-cells = <0>;
Yuan Yao1a414ae2016-03-15 14:36:44 +0800217 reg = <0x0 0x1550000 0x0 0x10000>,
Kuldeep Singh4c380872019-12-12 11:49:24 +0530218 <0x0 0x40000000 0x0 0x1000000>;
Yuan Yao1a414ae2016-03-15 14:36:44 +0800219 reg-names = "QuadSPI", "QuadSPI-memory";
Gong Qianyu760df892016-01-25 15:16:06 +0800220 status = "disabled";
221 };
Sriram Dash0b7a1fc2016-09-30 11:06:27 +0530222
223 usb0: usb3@2f00000 {
224 compatible = "fsl,layerscape-dwc3";
225 reg = <0x0 0x2f00000 0x0 0x10000>;
226 interrupts = <0 60 0x4>;
227 dr_mode = "host";
228 };
229
230 usb1: usb3@3000000 {
231 compatible = "fsl,layerscape-dwc3";
232 reg = <0x0 0x3000000 0x0 0x10000>;
233 interrupts = <0 61 0x4>;
234 dr_mode = "host";
235 };
236
237 usb2: usb3@3100000 {
238 compatible = "fsl,layerscape-dwc3";
239 reg = <0x0 0x3100000 0x0 0x10000>;
240 interrupts = <0 63 0x4>;
241 dr_mode = "host";
242 };
Minghuan Lian64d156b2016-12-13 14:54:13 +0800243
Wasim Khan05ee3882020-09-28 16:26:11 +0530244 pcie1: pcie@3400000 {
Minghuan Lian64d156b2016-12-13 14:54:13 +0800245 compatible = "fsl,ls-pcie", "snps,dw-pcie";
246 reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
247 0x00 0x03410000 0x0 0x10000 /* lut registers */
248 0x40 0x00000000 0x0 0x20000>; /* configuration space */
249 reg-names = "dbi", "lut", "config";
250 big-endian;
251 #address-cells = <3>;
252 #size-cells = <2>;
253 device_type = "pci";
254 bus-range = <0x0 0xff>;
255 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
256 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
257 };
258
Wasim Khan05ee3882020-09-28 16:26:11 +0530259 pcie2: pcie@3500000 {
Minghuan Lian64d156b2016-12-13 14:54:13 +0800260 compatible = "fsl,ls-pcie", "snps,dw-pcie";
261 reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
262 0x00 0x03510000 0x0 0x10000 /* lut registers */
263 0x48 0x00000000 0x0 0x20000>; /* configuration space */
264 reg-names = "dbi", "lut", "config";
265 big-endian;
266 #address-cells = <3>;
267 #size-cells = <2>;
268 device_type = "pci";
269 num-lanes = <2>;
270 bus-range = <0x0 0xff>;
271 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
272 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
273 };
274
Wasim Khan05ee3882020-09-28 16:26:11 +0530275 pcie3: pcie@3600000 {
Minghuan Lian64d156b2016-12-13 14:54:13 +0800276 compatible = "fsl,ls-pcie", "snps,dw-pcie";
277 reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
278 0x00 0x03610000 0x0 0x10000 /* lut registers */
279 0x50 0x00000000 0x0 0x20000>; /* configuration space */
280 reg-names = "dbi", "lut", "config";
281 big-endian;
282 #address-cells = <3>;
283 #size-cells = <2>;
284 device_type = "pci";
285 bus-range = <0x0 0xff>;
286 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
287 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
288 };
Peng Mad2c851b2018-08-01 11:35:14 +0800289
290 sata: sata@3200000 {
291 compatible = "fsl,ls1043a-ahci";
Peng Mae70d3622019-04-17 10:10:49 +0000292 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
293 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
294 reg-names = "sata-base", "ecc-addr";
Peng Mad2c851b2018-08-01 11:35:14 +0800295 interrupts = <0 69 4>;
296 clocks = <&clockgen 4 0>;
297 status = "disabled";
298 };
Gong Qianyu5e847792015-11-11 17:58:36 +0800299 };
300};