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git01.mediatek.com / filogic / uboot / d1c0eb950e0f20925624d5b3358bc1f9c9d551ea / . / drivers / serial / serial_rockchip.c
blob: f4e9422ed91c95e965f43b043f5be82db245586d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]2/*
3 * Copyright (c) 2015 Google, Inc
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]4 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <dm.h>
9#include <dt-structs.h>
10#include <ns16550.h>
11#include <serial.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +0800[diff] [blame]12#include <asm/arch-rockchip/clock.h>
Simon Glass95588622020-12-22 19:30:28 -0700[diff] [blame]13#include <dm/device-internal.h>
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]14
Simon Glassb75b15b2020-12-03 16:55:23 -0700[diff] [blame]15struct rockchip_uart_plat {
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]16#if CONFIG_IS_ENABLED(OF_PLATDATA)
Johan Jonkerd1c0eb92022-04-09 18:55:12 +0200[diff] [blame^]17 struct dtd_rockchip_uart dtplat;
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]18#endif
Simon Glassb75b15b2020-12-03 16:55:23 -0700[diff] [blame]19 struct ns16550_plat plat;
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]20};
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]21
22#if CONFIG_IS_ENABLED(OF_PLATDATA)
Johan Jonkerd1c0eb92022-04-09 18:55:12 +0200[diff] [blame^]23struct dtd_rockchip_uart *dtplat, s_dtplat;
Heiko Stübner2d76bfd2017-02-18 19:46:29 +0100[diff] [blame]24#endif
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]25
26static int rockchip_serial_probe(struct udevice *dev)
27{
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]28#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassb75b15b2020-12-03 16:55:23 -0700[diff] [blame]29 struct rockchip_uart_plat *plat = dev_get_plat(dev);
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]30
31 /* Create some new platform data for the standard driver */
32 plat->plat.base = plat->dtplat.reg[0];
33 plat->plat.reg_shift = plat->dtplat.reg_shift;
34 plat->plat.clock = plat->dtplat.clock_frequency;
Heiko Schocher06f108e2017-01-18 08:05:49 +0100[diff] [blame]35 plat->plat.fcr = UART_FCR_DEFVAL;
Simon Glass95588622020-12-22 19:30:28 -0700[diff] [blame]36 dev_set_plat(dev, &plat->plat);
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]37
38 return ns16550_serial_probe(dev);
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]39#else
40 return -ENODEV;
41#endif
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]42}
43
Johan Jonkerd1c0eb92022-04-09 18:55:12 +0200[diff] [blame^]44U_BOOT_DRIVER(rockchip_uart) = {
45 .name = "rockchip_uart",
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]46 .id = UCLASS_SERIAL,
Simon Glass119e7ef2020-12-22 19:30:18 -0700[diff] [blame]47 .priv_auto = sizeof(struct ns16550),
Simon Glassb75b15b2020-12-03 16:55:23 -0700[diff] [blame]48 .plat_auto = sizeof(struct rockchip_uart_plat),
Johan Jonkere7903162022-04-09 18:55:10 +0200[diff] [blame]49 .probe = rockchip_serial_probe,
50 .ops = &ns16550_serial_ops,
51 .flags = DM_FLAG_PRE_RELOC,
Simon Glassb3068ad2016-07-04 11:58:24 -0600[diff] [blame]52};
Johan Jonkerd1c0eb92022-04-09 18:55:12 +0200[diff] [blame^]53DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3066_uart)
54DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3188_uart)
55DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3288_uart)
56DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3328_uart)
57DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3368_uart)