Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Atmel Corporation |
| 3 | * Wenyou.Yang <wenyou.yang@atmel.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <atmel_hlcdc.h> |
Wenyou Yang | 113e1d1 | 2016-10-17 09:55:26 +0800 | [diff] [blame] | 10 | #include <debug_uart.h> |
Wenyou Yang | 3ce80fa | 2016-10-17 09:55:25 +0800 | [diff] [blame] | 11 | #include <dm.h> |
| 12 | #include <i2c.h> |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 13 | #include <lcd.h> |
| 14 | #include <mmc.h> |
| 15 | #include <net.h> |
| 16 | #include <netdev.h> |
| 17 | #include <spi.h> |
| 18 | #include <version.h> |
| 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/at91_common.h> |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 21 | #include <asm/arch/atmel_pio4.h> |
Wenyou Yang | 3acd9cc | 2016-02-01 18:18:21 +0800 | [diff] [blame] | 22 | #include <asm/arch/atmel_mpddrc.h> |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 23 | #include <asm/arch/atmel_usba_udc.h> |
| 24 | #include <asm/arch/atmel_sdhci.h> |
| 25 | #include <asm/arch/clk.h> |
| 26 | #include <asm/arch/gpio.h> |
| 27 | #include <asm/arch/sama5d2.h> |
| 28 | |
| 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 31 | static void board_usb_hw_init(void) |
| 32 | { |
| 33 | atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); |
| 34 | } |
| 35 | |
| 36 | #ifdef CONFIG_LCD |
| 37 | vidinfo_t panel_info = { |
| 38 | .vl_col = 480, |
| 39 | .vl_row = 272, |
| 40 | .vl_clk = 9000000, |
| 41 | .vl_bpix = LCD_BPP, |
| 42 | .vl_tft = 1, |
| 43 | .vl_hsync_len = 41, |
| 44 | .vl_left_margin = 2, |
| 45 | .vl_right_margin = 2, |
| 46 | .vl_vsync_len = 11, |
| 47 | .vl_upper_margin = 2, |
| 48 | .vl_lower_margin = 2, |
| 49 | .mmio = ATMEL_BASE_LCDC, |
| 50 | }; |
| 51 | |
| 52 | /* No power up/down pin for the LCD pannel */ |
| 53 | void lcd_enable(void) { /* Empty! */ } |
| 54 | void lcd_disable(void) { /* Empty! */ } |
| 55 | |
| 56 | unsigned int has_lcdc(void) |
| 57 | { |
| 58 | return 1; |
| 59 | } |
| 60 | |
| 61 | static void board_lcd_hw_init(void) |
| 62 | { |
| 63 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ |
| 64 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ |
| 65 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ |
| 66 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ |
| 67 | atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ |
| 68 | atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ |
| 69 | |
| 70 | /* LCDDAT0 */ |
| 71 | /* LCDDAT1 */ |
| 72 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ |
| 73 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ |
| 74 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ |
| 75 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ |
| 76 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ |
| 77 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ |
| 78 | |
| 79 | /* LCDDAT8 */ |
| 80 | /* LCDDAT9 */ |
| 81 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ |
| 82 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ |
| 83 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ |
| 84 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ |
| 85 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ |
| 86 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ |
| 87 | |
| 88 | /* LCDD16 */ |
| 89 | /* LCDD17 */ |
| 90 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ |
| 91 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ |
| 92 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ |
| 93 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ |
| 94 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ |
| 95 | atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ |
| 96 | |
| 97 | at91_periph_clk_enable(ATMEL_ID_LCDC); |
| 98 | } |
| 99 | |
| 100 | #ifdef CONFIG_LCD_INFO |
| 101 | void lcd_show_board_info(void) |
| 102 | { |
| 103 | ulong dram_size; |
| 104 | int i; |
| 105 | char temp[32]; |
| 106 | |
| 107 | lcd_printf("%s\n", U_BOOT_VERSION); |
| 108 | lcd_printf("2015 ATMEL Corp\n"); |
| 109 | lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), |
| 110 | strmhz(temp, get_cpu_clk_rate())); |
| 111 | |
| 112 | dram_size = 0; |
| 113 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) |
| 114 | dram_size += gd->bd->bi_dram[i].size; |
| 115 | |
| 116 | lcd_printf("%ld MB SDRAM\n", dram_size >> 20); |
| 117 | } |
| 118 | #endif /* CONFIG_LCD_INFO */ |
| 119 | #endif /* CONFIG_LCD */ |
| 120 | |
| 121 | static void board_gmac_hw_init(void) |
| 122 | { |
| 123 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ |
| 124 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ |
| 125 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ |
| 126 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ |
| 127 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ |
| 128 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ |
| 129 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ |
| 130 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ |
| 131 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ |
| 132 | atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ |
| 133 | |
| 134 | at91_periph_clk_enable(ATMEL_ID_GMAC); |
| 135 | } |
| 136 | |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 137 | static void board_uart1_hw_init(void) |
| 138 | { |
| 139 | atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ |
| 140 | atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ |
| 141 | |
| 142 | at91_periph_clk_enable(ATMEL_ID_UART1); |
| 143 | } |
| 144 | |
Wenyou Yang | 113e1d1 | 2016-10-17 09:55:26 +0800 | [diff] [blame] | 145 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT |
| 146 | void board_debug_uart_init(void) |
| 147 | { |
| 148 | board_uart1_hw_init(); |
| 149 | } |
| 150 | #endif |
| 151 | |
| 152 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 153 | int board_early_init_f(void) |
| 154 | { |
Wenyou Yang | 113e1d1 | 2016-10-17 09:55:26 +0800 | [diff] [blame] | 155 | #ifdef CONFIG_DEBUG_UART |
| 156 | debug_uart_init(); |
| 157 | #else |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 158 | board_uart1_hw_init(); |
Wenyou Yang | 113e1d1 | 2016-10-17 09:55:26 +0800 | [diff] [blame] | 159 | #endif |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 160 | |
| 161 | return 0; |
| 162 | } |
Wenyou Yang | 113e1d1 | 2016-10-17 09:55:26 +0800 | [diff] [blame] | 163 | #endif |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 164 | |
| 165 | int board_init(void) |
| 166 | { |
| 167 | /* address of boot parameters */ |
| 168 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 169 | |
Wenyou Yang | c64a75a | 2015-10-30 09:55:52 +0800 | [diff] [blame] | 170 | #ifdef CONFIG_MACB |
| 171 | board_gmac_hw_init(); |
| 172 | #endif |
| 173 | #ifdef CONFIG_LCD |
| 174 | board_lcd_hw_init(); |
| 175 | #endif |
| 176 | #ifdef CONFIG_CMD_USB |
| 177 | board_usb_hw_init(); |
| 178 | #endif |
| 179 | #ifdef CONFIG_USB_GADGET_ATMEL_USBA |
| 180 | at91_udp_hw_init(); |
| 181 | #endif |
| 182 | |
| 183 | return 0; |
| 184 | } |
| 185 | |
| 186 | int dram_init(void) |
| 187 | { |
| 188 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
| 189 | CONFIG_SYS_SDRAM_SIZE); |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | int board_eth_init(bd_t *bis) |
| 194 | { |
| 195 | int rc = 0; |
| 196 | |
| 197 | #ifdef CONFIG_MACB |
| 198 | rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); |
| 199 | #endif |
| 200 | |
| 201 | #ifdef CONFIG_USB_GADGET_ATMEL_USBA |
| 202 | usba_udc_probe(&pdata); |
| 203 | #ifdef CONFIG_USB_ETH_RNDIS |
| 204 | usb_eth_initialize(bis); |
| 205 | #endif |
| 206 | #endif |
| 207 | |
| 208 | return rc; |
| 209 | } |
Wenyou Yang | 3acd9cc | 2016-02-01 18:18:21 +0800 | [diff] [blame] | 210 | |
Wenyou Yang | 3ce80fa | 2016-10-17 09:55:25 +0800 | [diff] [blame] | 211 | #ifdef CONFIG_CMD_I2C |
| 212 | static int set_ethaddr_from_eeprom(void) |
| 213 | { |
| 214 | const int ETH_ADDR_LEN = 6; |
| 215 | unsigned char ethaddr[ETH_ADDR_LEN]; |
| 216 | const char *ETHADDR_NAME = "ethaddr"; |
| 217 | struct udevice *bus, *dev; |
| 218 | |
| 219 | if (getenv(ETHADDR_NAME)) |
| 220 | return 0; |
| 221 | |
| 222 | if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) { |
| 223 | printf("Cannot find I2C bus 1\n"); |
| 224 | return -1; |
| 225 | } |
| 226 | |
| 227 | if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) { |
| 228 | printf("Failed to probe I2C chip\n"); |
| 229 | return -1; |
| 230 | } |
| 231 | |
| 232 | if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) { |
| 233 | printf("Failed to read ethernet address from EEPROM\n"); |
| 234 | return -1; |
| 235 | } |
| 236 | |
| 237 | if (!is_valid_ethaddr(ethaddr)) { |
| 238 | printf("The ethernet address read from EEPROM is not valid!\n"); |
| 239 | return -1; |
| 240 | } |
| 241 | |
| 242 | return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr); |
| 243 | } |
| 244 | #else |
| 245 | static int set_ethaddr_from_eeprom(void) |
| 246 | { |
| 247 | return 0; |
| 248 | } |
| 249 | #endif |
| 250 | |
| 251 | #ifdef CONFIG_MISC_INIT_R |
| 252 | int misc_init_r(void) |
| 253 | { |
| 254 | set_ethaddr_from_eeprom(); |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | #endif |
| 259 | |
Wenyou Yang | 3acd9cc | 2016-02-01 18:18:21 +0800 | [diff] [blame] | 260 | /* SPL */ |
| 261 | #ifdef CONFIG_SPL_BUILD |
| 262 | void spl_board_init(void) |
| 263 | { |
Wenyou Yang | 3acd9cc | 2016-02-01 18:18:21 +0800 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | static void ddrc_conf(struct atmel_mpddrc_config *ddrc) |
| 267 | { |
| 268 | ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); |
| 269 | |
| 270 | ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | |
| 271 | ATMEL_MPDDRC_CR_NR_ROW_14 | |
| 272 | ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | |
| 273 | ATMEL_MPDDRC_CR_DIC_DS | |
| 274 | ATMEL_MPDDRC_CR_DIS_DLL | |
| 275 | ATMEL_MPDDRC_CR_NB_8BANKS | |
| 276 | ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | |
| 277 | ATMEL_MPDDRC_CR_UNAL_SUPPORTED); |
| 278 | |
| 279 | ddrc->rtr = 0x511; |
| 280 | |
| 281 | ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | |
| 282 | 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | |
| 283 | 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | |
| 284 | 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | |
| 285 | 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | |
| 286 | 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | |
| 287 | 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | |
| 288 | 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); |
| 289 | |
| 290 | ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | |
| 291 | 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | |
| 292 | 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | |
| 293 | 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET); |
| 294 | |
| 295 | ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | |
| 296 | 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | |
| 297 | 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | |
| 298 | 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | |
| 299 | 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET); |
| 300 | } |
| 301 | |
| 302 | void mem_init(void) |
| 303 | { |
| 304 | struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
| 305 | struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; |
| 306 | struct atmel_mpddrc_config ddrc_config; |
| 307 | u32 reg; |
| 308 | |
| 309 | ddrc_conf(&ddrc_config); |
| 310 | |
| 311 | at91_periph_clk_enable(ATMEL_ID_MPDDRC); |
| 312 | writel(AT91_PMC_DDR, &pmc->scer); |
| 313 | |
| 314 | reg = readl(&mpddrc->io_calibr); |
| 315 | reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; |
| 316 | reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; |
| 317 | reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; |
| 318 | reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); |
| 319 | writel(reg, &mpddrc->io_calibr); |
| 320 | |
| 321 | writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, |
| 322 | &mpddrc->rd_data_path); |
| 323 | |
| 324 | ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); |
| 325 | |
| 326 | writel(0x3, &mpddrc->cal_mr4); |
| 327 | writel(64, &mpddrc->tim_cal); |
| 328 | } |
| 329 | |
| 330 | void at91_pmc_init(void) |
| 331 | { |
| 332 | struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
| 333 | u32 tmp; |
| 334 | |
| 335 | tmp = AT91_PMC_PLLAR_29 | |
| 336 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | |
| 337 | AT91_PMC_PLLXR_MUL(82) | |
| 338 | AT91_PMC_PLLXR_DIV(1); |
| 339 | at91_plla_init(tmp); |
| 340 | |
| 341 | writel(0x0 << 8, &pmc->pllicpr); |
| 342 | |
| 343 | tmp = AT91_PMC_MCKR_H32MXDIV | |
| 344 | AT91_PMC_MCKR_PLLADIV_2 | |
| 345 | AT91_PMC_MCKR_MDIV_3 | |
| 346 | AT91_PMC_MCKR_CSS_PLLA; |
| 347 | at91_mck_init(tmp); |
| 348 | } |
| 349 | #endif |