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Michal Simek4b066a12018-08-22 14:55:27 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Michal Simek4b066a12018-08-22 14:55:27 +02009#include <fdtdec.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Michal Simek4b066a12018-08-22 14:55:27 +020011#include <malloc.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070012#include <time.h>
Michal Simek4b066a12018-08-22 14:55:27 +020013#include <asm/io.h>
14#include <asm/arch/hardware.h>
Michal Simek21eb5cc2019-04-29 09:39:09 -070015#include <asm/arch/sys_proto.h>
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +053016#include <dm/device.h>
17#include <dm/uclass.h>
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053018#include <versalpl.h>
Siva Durga Prasad Paladuguc5cf9d12019-08-05 23:28:30 +053019#include <linux/sizes.h>
Michal Simek4b066a12018-08-22 14:55:27 +020020
21DECLARE_GLOBAL_DATA_PTR;
22
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053023#if defined(CONFIG_FPGA_VERSALPL)
24static xilinx_desc versalpl = XILINX_VERSAL_DESC;
25#endif
26
Michal Simek4b066a12018-08-22 14:55:27 +020027int board_init(void)
28{
29 printf("EL Level:\tEL%d\n", current_el());
30
Siva Durga Prasad Paladugub7398972019-08-05 15:54:59 +053031#if defined(CONFIG_FPGA_VERSALPL)
32 fpga_init();
33 fpga_add(fpga_xilinx, &versalpl);
34#endif
35
Michal Simek4b066a12018-08-22 14:55:27 +020036 return 0;
37}
38
39int board_early_init_r(void)
40{
Michal Simek19f6c972019-01-28 11:08:00 +010041 u32 val;
Michal Simek4b066a12018-08-22 14:55:27 +020042
Michal Simek19f6c972019-01-28 11:08:00 +010043 if (current_el() != 3)
44 return 0;
Michal Simek4b066a12018-08-22 14:55:27 +020045
Michal Simekf56f7d12019-01-28 11:12:41 +010046 debug("iou_switch ctrl div0 %x\n",
47 readl(&crlapb_base->iou_switch_ctrl));
48
Michal Simek19f6c972019-01-28 11:08:00 +010049 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
Michal Simekf56f7d12019-01-28 11:12:41 +010050 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
Michal Simek19f6c972019-01-28 11:08:00 +010051 &crlapb_base->iou_switch_ctrl);
Michal Simek4b066a12018-08-22 14:55:27 +020052
Michal Simek19f6c972019-01-28 11:08:00 +010053 /* Global timer init - Program time stamp reference clk */
54 val = readl(&crlapb_base->timestamp_ref_ctrl);
55 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
56 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek4b066a12018-08-22 14:55:27 +020057
Michal Simek19f6c972019-01-28 11:08:00 +010058 debug("ref ctrl 0x%x\n",
59 readl(&crlapb_base->timestamp_ref_ctrl));
Michal Simek4b066a12018-08-22 14:55:27 +020060
Michal Simek19f6c972019-01-28 11:08:00 +010061 /* Clear reset of timestamp reg */
62 writel(0, &crlapb_base->rst_timestamp);
Michal Simek4b066a12018-08-22 14:55:27 +020063
Michal Simek19f6c972019-01-28 11:08:00 +010064 /*
65 * Program freq register in System counter and
66 * enable system counter.
67 */
68 writel(COUNTER_FREQUENCY,
69 &iou_scntr_secure->base_frequency_id_register);
Michal Simek4b066a12018-08-22 14:55:27 +020070
Michal Simek19f6c972019-01-28 11:08:00 +010071 debug("counter val 0x%x\n",
72 readl(&iou_scntr_secure->base_frequency_id_register));
73
74 writel(IOU_SCNTRS_CONTROL_EN,
75 &iou_scntr_secure->counter_control_register);
Michal Simek4b066a12018-08-22 14:55:27 +020076
Michal Simek19f6c972019-01-28 11:08:00 +010077 debug("scntrs control 0x%x\n",
78 readl(&iou_scntr_secure->counter_control_register));
79 debug("timer 0x%llx\n", get_ticks());
80 debug("timer 0x%llx\n", get_ticks());
Michal Simek4b066a12018-08-22 14:55:27 +020081
82 return 0;
83}
84
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +053085int board_late_init(void)
86{
87 u32 reg = 0;
88 u8 bootmode;
89 struct udevice *dev;
90 int bootseq = -1;
91 int bootseq_len = 0;
92 int env_targets_len = 0;
93 const char *mode;
94 char *new_targets;
95 char *env_targets;
Siva Durga Prasad Paladuguc5cf9d12019-08-05 23:28:30 +053096 ulong initrd_hi;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +053097
98 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
99 debug("Saved variables - Skipping\n");
100 return 0;
101 }
102
103 reg = readl(&crp_base->boot_mode_usr);
104
105 if (reg >> BOOT_MODE_ALT_SHIFT)
106 reg >>= BOOT_MODE_ALT_SHIFT;
107
108 bootmode = reg & BOOT_MODES_MASK;
109
110 puts("Bootmode: ");
111 switch (bootmode) {
T Karthik Reddyfacca9a2019-07-11 16:07:57 +0530112 case USB_MODE:
113 puts("USB_MODE\n");
114 mode = "dfu_usb";
115 break;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530116 case JTAG_MODE:
117 puts("JTAG_MODE\n");
Siva Durga Prasad Paladugu00784e02019-06-25 17:13:14 +0530118 mode = "jtag pxe dhcp";
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530119 break;
120 case QSPI_MODE_24BIT:
121 puts("QSPI_MODE_24\n");
122 mode = "xspi0";
123 break;
124 case QSPI_MODE_32BIT:
125 puts("QSPI_MODE_32\n");
126 mode = "xspi0";
127 break;
128 case OSPI_MODE:
129 puts("OSPI_MODE\n");
130 mode = "xspi0";
131 break;
132 case EMMC_MODE:
133 puts("EMMC_MODE\n");
T Karthik Reddybc2b9642019-12-16 04:44:26 -0700134 if (uclass_get_device_by_name(UCLASS_MMC,
135 "sdhci@f1050000", &dev)) {
136 puts("Boot from EMMC but without SD1 enabled!\n");
137 return -1;
138 }
139 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
140 mode = "mmc";
141 bootseq = dev->seq;
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530142 break;
143 case SD_MODE:
144 puts("SD_MODE\n");
145 if (uclass_get_device_by_name(UCLASS_MMC,
146 "sdhci@f1040000", &dev)) {
147 puts("Boot from SD0 but without SD0 enabled!\n");
148 return -1;
149 }
150 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
151
152 mode = "mmc";
153 bootseq = dev->seq;
154 break;
155 case SD1_LSHFT_MODE:
156 puts("LVL_SHFT_");
157 /* fall through */
158 case SD_MODE1:
159 puts("SD_MODE1\n");
160 if (uclass_get_device_by_name(UCLASS_MMC,
161 "sdhci@f1050000", &dev)) {
162 puts("Boot from SD1 but without SD1 enabled!\n");
163 return -1;
164 }
165 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
166
167 mode = "mmc";
168 bootseq = dev->seq;
169 break;
170 default:
171 mode = "";
172 printf("Invalid Boot Mode:0x%x\n", bootmode);
173 break;
174 }
175
176 if (bootseq >= 0) {
177 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
178 debug("Bootseq len: %x\n", bootseq_len);
179 }
180
181 /*
182 * One terminating char + one byte for space between mode
183 * and default boot_targets
184 */
185 env_targets = env_get("boot_targets");
186 if (env_targets)
187 env_targets_len = strlen(env_targets);
188
189 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
190 bootseq_len);
191 if (!new_targets)
192 return -ENOMEM;
193
194 if (bootseq >= 0)
195 sprintf(new_targets, "%s%x %s", mode, bootseq,
196 env_targets ? env_targets : "");
197 else
198 sprintf(new_targets, "%s %s", mode,
199 env_targets ? env_targets : "");
200
201 env_set("boot_targets", new_targets);
202
Siva Durga Prasad Paladuguc5cf9d12019-08-05 23:28:30 +0530203 initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
204 initrd_hi = round_down(initrd_hi, SZ_16M);
205 env_set_addr("initrd_high", (void *)initrd_hi);
206
T Karthik Reddy5fa6c1e2019-12-18 03:34:41 -0700207 env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
208
Siva Durga Prasad Paladugu37c2ff82019-01-31 17:28:14 +0530209 return 0;
210}
211
Michal Simek4b066a12018-08-22 14:55:27 +0200212int dram_init_banksize(void)
213{
Michal Simek21eb5cc2019-04-29 09:39:09 -0700214 int ret;
215
216 ret = fdtdec_setup_memory_banksize();
217 if (ret)
218 return ret;
219
220 mem_map_fill();
Michal Simek4b066a12018-08-22 14:55:27 +0200221
222 return 0;
223}
224
225int dram_init(void)
226{
227 if (fdtdec_setup_mem_size_base() != 0)
228 return -EINVAL;
229
230 return 0;
231}
232
233void reset_cpu(ulong addr)
234{
235}