blob: b4201e76d1c7bf896de9ac1d820dcaa769c9aa5c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Feng Li39e112d2016-11-03 14:15:17 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Feng Li39e112d2016-11-03 14:15:17 +08004 */
5
6#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07007#include <clock_legacy.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07008#include <fdt_support.h>
Simon Glassa7b51302019-11-14 12:57:46 -07009#include <init.h>
Feng Li39e112d2016-11-03 14:15:17 +080010#include <asm/arch/immap_ls102xa.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
13#include <asm/arch/ls102xa_stream_id.h>
14
15#include <asm/arch/ls102xa_devdis.h>
16#include <asm/arch/ls102xa_soc.h>
Feng Li39e112d2016-11-03 14:15:17 +080017#include <fsl_csu.h>
Feng Li39e112d2016-11-03 14:15:17 +080018#include <fsl_immap.h>
19#include <netdev.h>
20#include <fsl_mdio.h>
21#include <tsec.h>
22#include <spl.h>
23
24#include <fsl_validate.h>
25#include "../common/sleep.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#define DDR_SIZE 0x40000000
30
31
32int checkboard(void)
33{
34 puts("Board: LS1021AIOT\n");
35
36#ifndef CONFIG_QSPI_BOOT
37 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
38 u32 cpldrev;
39
40 cpldrev = in_be32(&dcfg->gpporcr1);
41
42 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
43 0xf));
44#endif
45 return 0;
46}
47
48void ddrmc_init(void)
49{
50 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
51 u32 temp_sdram_cfg, tmp;
52
53 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
54
55 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
56 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
57
58 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
59 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
60 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
61 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
62 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
63 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
64
65 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
66 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
67
68 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
69 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
70
71 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
72
73 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
74
75 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
76 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
77
78 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
79
80 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
81 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
82
83 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
84
85 /* DDR erratum A-009942 */
86 tmp = in_be32(&ddr->debug[28]);
87 out_be32(&ddr->debug[28], tmp | 0x0070006f);
88
89 udelay(500);
90
91 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
92
93 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
94}
95
96int dram_init(void)
97{
98#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
99 ddrmc_init();
100#endif
101
Alison Wangd6be97b2019-03-06 14:49:14 +0800102 erratum_a008850_post();
103
Feng Li39e112d2016-11-03 14:15:17 +0800104 gd->ram_size = DDR_SIZE;
105 return 0;
106}
107
Feng Li39e112d2016-11-03 14:15:17 +0800108#ifdef CONFIG_TSEC_ENET
109int board_eth_init(bd_t *bis)
110{
111 struct fsl_pq_mdio_info mdio_info;
112 struct tsec_info_struct tsec_info[4];
113 int num = 0;
114
115#ifdef CONFIG_TSEC1
116 SET_STD_TSEC_INFO(tsec_info[num], 1);
117 if (is_serdes_configured(SGMII_TSEC1)) {
118 puts("eTSEC1 is in sgmii mode.\n");
119 tsec_info[num].flags |= TSEC_SGMII;
120 }
121 num++;
122#endif
123#ifdef CONFIG_TSEC2
124 SET_STD_TSEC_INFO(tsec_info[num], 2);
125 if (is_serdes_configured(SGMII_TSEC2)) {
126 puts("eTSEC2 is in sgmii mode.\n");
127 tsec_info[num].flags |= TSEC_SGMII;
128 }
129 num++;
130#endif
131 if (!num) {
132 printf("No TSECs initialized\n");
133 return 0;
134 }
135
136 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
137 mdio_info.name = DEFAULT_MII_NAME;
138 fsl_pq_mdio_init(bis, &mdio_info);
139
140 tsec_eth_init(bis, tsec_info, num);
141
142 return pci_eth_init(bis);
143}
144#endif
145
146int board_early_init_f(void)
147{
148 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
149
150#ifdef CONFIG_TSEC_ENET
151 /* clear BD & FR bits for BE BD's and frame data */
152 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
153 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
154
155#endif
156
157 arch_soc_init();
158
159 return 0;
160}
161
162#ifdef CONFIG_SPL_BUILD
163void board_init_f(ulong dummy)
164{
165 /* Clear the BSS */
166 memset(__bss_start, 0, __bss_end - __bss_start);
167
168 get_clocks();
169
170 preloader_console_init();
171
172 dram_init();
173
174 /* Allow OCRAM access permission as R/W */
175
176#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
177 enable_layerscape_ns_access();
178#endif
179
180 board_init_r(NULL, 0);
181}
182#endif
183
184int board_init(void)
185{
186#ifndef CONFIG_SYS_FSL_NO_SERDES
187 fsl_serdes_init();
188#endif
189
190 ls102xa_smmu_stream_id_init();
191
Feng Li39e112d2016-11-03 14:15:17 +0800192 return 0;
193}
194
195#ifdef CONFIG_BOARD_LATE_INIT
196int board_late_init(void)
197{
Feng Li39e112d2016-11-03 14:15:17 +0800198 return 0;
199}
200#endif
201
202#if defined(CONFIG_MISC_INIT_R)
203int misc_init_r(void)
204{
205#ifdef CONFIG_FSL_DEVICE_DISABLE
206 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
207
208#endif
209
210#ifdef CONFIG_FSL_CAAM
211 return sec_init();
212#endif
213}
214#endif
215
216int ft_board_setup(void *blob, bd_t *bd)
217{
218 ft_cpu_setup(blob, bd);
219
220#ifdef CONFIG_PCI
221 ft_pci_setup(blob, bd);
222#endif
223
224 return 0;
225}
226
227void flash_write16(u16 val, void *addr)
228{
229 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
230
231 __raw_writew(shftval, addr);
232}
233
234u16 flash_read16(void *addr)
235{
236 u16 val = __raw_readw(addr);
237
238 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
239}