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git01.mediatek.com / filogic / uboot / d18a578637aeaa2591588f106d76d2d6c84be5f5 / . / drivers / pinctrl / renesas / pfc-r8a7795.c
blob: 898f837950d00e12b99720da032122c211b4528f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
3 * R8A7795 ES2.0+ processor support - PFC hardware block.
4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <dm/pinctrl.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
19
20#define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]22 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
33/*
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
36 */
37
38/* GPSR0 */
39#define GPSR0_15 F_(D15, IP7_11_8)
40#define GPSR0_14 F_(D14, IP7_7_4)
41#define GPSR0_13 F_(D13, IP7_3_0)
42#define GPSR0_12 F_(D12, IP6_31_28)
43#define GPSR0_11 F_(D11, IP6_27_24)
44#define GPSR0_10 F_(D10, IP6_23_20)
45#define GPSR0_9 F_(D9, IP6_19_16)
46#define GPSR0_8 F_(D8, IP6_15_12)
47#define GPSR0_7 F_(D7, IP6_11_8)
48#define GPSR0_6 F_(D6, IP6_7_4)
49#define GPSR0_5 F_(D5, IP6_3_0)
50#define GPSR0_4 F_(D4, IP5_31_28)
51#define GPSR0_3 F_(D3, IP5_27_24)
52#define GPSR0_2 F_(D2, IP5_23_20)
53#define GPSR0_1 F_(D1, IP5_19_16)
54#define GPSR0_0 F_(D0, IP5_15_12)
55
56/* GPSR1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]57#define GPSR1_28 FM(CLKOUT)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146#define GPSR5_22 FM(MSIOF0_RXD)
147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148#define GPSR5_20 FM(MSIOF0_TXD)
149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151#define GPSR5_17 FM(MSIOF0_SCK)
152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]160#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]164#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
169
170/* GPSR6 */
171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
203
204/* GPSR7 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]205#define GPSR7_3 FM(GP7_03)
206#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]315#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]319#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]371 GPSR1_28 GPSR6_28 \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]466#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]474#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]502#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
503#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
506#define PINMUX_MOD_SELS \
507\
508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
514MOD_SEL0_23 MOD_SEL1_23_22_21 \
515MOD_SEL0_22 \
516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
522 MOD_SEL1_15_14 \
523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
528MOD_SEL0_9_8 MOD_SEL1_9 \
529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]551 FM(PRESETOUT) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]555#define PINMUX_PHYS \
556 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
557
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]558enum {
559 PINMUX_RESERVED = 0,
560
561 PINMUX_DATA_BEGIN,
562 GP_ALL(DATA),
563 PINMUX_DATA_END,
564
565#define F_(x, y)
566#define FM(x) FN_##x,
567 PINMUX_FUNCTION_BEGIN,
568 GP_ALL(FN),
569 PINMUX_GPSR
570 PINMUX_IPSR
571 PINMUX_MOD_SELS
572 PINMUX_FUNCTION_END,
573#undef F_
574#undef FM
575
576#define F_(x, y)
577#define FM(x) x##_MARK,
578 PINMUX_MARK_BEGIN,
579 PINMUX_GPSR
580 PINMUX_IPSR
581 PINMUX_MOD_SELS
582 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]583 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]584 PINMUX_MARK_END,
585#undef F_
586#undef FM
587};
588
589static const u16 pinmux_data[] = {
590 PINMUX_DATA_GP_ALL(),
591
592 PINMUX_SINGLE(AVS1),
593 PINMUX_SINGLE(AVS2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]594 PINMUX_SINGLE(CLKOUT),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]595 PINMUX_SINGLE(GP7_02),
596 PINMUX_SINGLE(GP7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
604 /* IPSR0 */
605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]620 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
621 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
622 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
624 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]625
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]626 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
627 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
628 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
629 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
633 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
634 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
638
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
646
647 /* IPSR1 */
648 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
649 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
650 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
651 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
653 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
654
655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]657 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
658 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
660 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
661
662 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
663 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
668
669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]671 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
672 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
673 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
674 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
675 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
676
677 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
678 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]682 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
683 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
684 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
685 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]686 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]687
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]688 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
689 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
690 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
691 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]692
693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
728
729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
736
737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
744
745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
752
753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
766
767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
771
772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
788
789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
795
796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
802
803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
809
810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
814
815 /* IPSR4 */
816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
883
884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
889
890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
895
896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
900
901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
905
906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
910
911 /* IPSR6 */
912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
916
917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
921
922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
926
927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
933
934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
939
940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
947
948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
955
956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
962
963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
970
971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
978
979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
994
995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
999
1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1004
1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1015
1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1019
1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1025
1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1039
1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1046
1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1053
1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1057
1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1060
1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1063
1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1066
1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1069
1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1072
1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1076
1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1079
1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1083
1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1086
1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1089
1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1092
1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1095
1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1099
1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1103
1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1107
1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1123 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1124 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1125 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1126
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1127 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1128 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1129 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1130
1131 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1132 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1134 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1135 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1136 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1139 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1141
1142 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1143 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1144 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1147
1148 /* IPSR12 */
1149 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1150 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1151 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1153 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1154
1155 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1156 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1158 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1160 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1161 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1162 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1163
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1164 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1165 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1167 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1168 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1169 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1170 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1171 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1172
1173 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1177 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1178
1179 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1183 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1184
1185 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1186 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1188 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1190 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1191 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1192
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1193 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1194 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1195 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1196 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1198 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1199 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1200
1201 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1202 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1204 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1206 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1207 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1208
1209 /* IPSR13 */
1210 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1212 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1214 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1215 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1216
1217 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1219 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1221 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1222 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1223
1224 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1226 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1227 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1228 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1231 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1232
1233 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1234 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1235 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1236 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1239
1240 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1241 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1242 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1243 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1245 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1246
1247 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1248 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1249 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1250 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1251 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1253 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1254 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1255
1256 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1257 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1258 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1259 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1260 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1262 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1263
1264 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1265 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1266 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1267 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1268
1269 /* IPSR14 */
1270 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1271 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1272 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1273 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1274 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1275 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1276 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1277 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1278
1279 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1280 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1282 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1283 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1284 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1285 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1286 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1287
1288 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1289 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1290 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1291
1292 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1293 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1294 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1295 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1296
1297 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1298 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1299 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1300
1301 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1302 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1303
1304 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1305 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1306
1307 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1308 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1309
1310 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1311 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1312
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1314 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1315
1316 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1317 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1318 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1319
1320 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1321 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1323 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1324
1325 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1326 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1332
1333 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1334 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1340
1341 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1342 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1348
1349 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1350 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1356
1357 /* IPSR16 */
1358 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1359 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1360 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1361
1362 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1363 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1364 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1365
1366 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1367 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1368 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1369
1370 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1371 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1377
1378 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1379 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1385
1386 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1387 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1388 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1389 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1394
1395 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1396 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1400 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1402
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1403 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1405 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1407 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1408 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1409 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1410 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1411
1412 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1413 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1414
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1415 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1416 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1418 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1419 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1420
1421 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1422 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1423 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1425 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1427 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1428
1429 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1430 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1431 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1433 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1434 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1435
1436 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1438 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1439 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1441 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1443 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1444 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1445
1446 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1447 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1448 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1449 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1451 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1454 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1455
1456 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1457 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1458 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1459 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1461 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1462 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1463 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1464 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1465 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1466 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1467
1468 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1469 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1470 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1471 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1473 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1474 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1475 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1476 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1477
1478 /* IPSR18 */
1479 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1480 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1481 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1482 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1484 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1485 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1487 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1488
1489 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1490 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1491 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1492 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1495 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1497 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1498
1499/*
1500 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1501 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1502 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1503 * core will do the right thing and skip trying to mux the pin
1504 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1505 */
1506#define FM(x) PINMUX_DATA(x##_MARK, 0),
1507 PINMUX_STATIC
1508#undef FM
1509};
1510
1511/*
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1512 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1513 * Physical layout rows: A - AW, cols: 1 - 39.
1514 */
1515#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1516#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1517#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1518#define PIN_NONE U16_MAX
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1519
1520static const struct sh_pfc_pin pinmux_pins[] = {
1521 PINMUX_GPIO_GP_ALL(),
1522
1523 /*
1524 * Pins not associated with a GPIO port.
1525 *
1526 * The pin positions are different between different r8a7795
1527 * packages, all that is needed for the pfc driver is a unique
1528 * number for each pin. To this end use the pin layout from
1529 * R-Car H3SiP to calculate a unique number for each pin.
1530 */
1531 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1546 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1574};
1575
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1576/* - AUDIO CLOCK ------------------------------------------------------------ */
1577static const unsigned int audio_clk_a_a_pins[] = {
1578 /* CLK A */
1579 RCAR_GP_PIN(6, 22),
1580};
1581static const unsigned int audio_clk_a_a_mux[] = {
1582 AUDIO_CLKA_A_MARK,
1583};
1584static const unsigned int audio_clk_a_b_pins[] = {
1585 /* CLK A */
1586 RCAR_GP_PIN(5, 4),
1587};
1588static const unsigned int audio_clk_a_b_mux[] = {
1589 AUDIO_CLKA_B_MARK,
1590};
1591static const unsigned int audio_clk_a_c_pins[] = {
1592 /* CLK A */
1593 RCAR_GP_PIN(5, 19),
1594};
1595static const unsigned int audio_clk_a_c_mux[] = {
1596 AUDIO_CLKA_C_MARK,
1597};
1598static const unsigned int audio_clk_b_a_pins[] = {
1599 /* CLK B */
1600 RCAR_GP_PIN(5, 12),
1601};
1602static const unsigned int audio_clk_b_a_mux[] = {
1603 AUDIO_CLKB_A_MARK,
1604};
1605static const unsigned int audio_clk_b_b_pins[] = {
1606 /* CLK B */
1607 RCAR_GP_PIN(6, 23),
1608};
1609static const unsigned int audio_clk_b_b_mux[] = {
1610 AUDIO_CLKB_B_MARK,
1611};
1612static const unsigned int audio_clk_c_a_pins[] = {
1613 /* CLK C */
1614 RCAR_GP_PIN(5, 21),
1615};
1616static const unsigned int audio_clk_c_a_mux[] = {
1617 AUDIO_CLKC_A_MARK,
1618};
1619static const unsigned int audio_clk_c_b_pins[] = {
1620 /* CLK C */
1621 RCAR_GP_PIN(5, 0),
1622};
1623static const unsigned int audio_clk_c_b_mux[] = {
1624 AUDIO_CLKC_B_MARK,
1625};
1626static const unsigned int audio_clkout_a_pins[] = {
1627 /* CLKOUT */
1628 RCAR_GP_PIN(5, 18),
1629};
1630static const unsigned int audio_clkout_a_mux[] = {
1631 AUDIO_CLKOUT_A_MARK,
1632};
1633static const unsigned int audio_clkout_b_pins[] = {
1634 /* CLKOUT */
1635 RCAR_GP_PIN(6, 28),
1636};
1637static const unsigned int audio_clkout_b_mux[] = {
1638 AUDIO_CLKOUT_B_MARK,
1639};
1640static const unsigned int audio_clkout_c_pins[] = {
1641 /* CLKOUT */
1642 RCAR_GP_PIN(5, 3),
1643};
1644static const unsigned int audio_clkout_c_mux[] = {
1645 AUDIO_CLKOUT_C_MARK,
1646};
1647static const unsigned int audio_clkout_d_pins[] = {
1648 /* CLKOUT */
1649 RCAR_GP_PIN(5, 21),
1650};
1651static const unsigned int audio_clkout_d_mux[] = {
1652 AUDIO_CLKOUT_D_MARK,
1653};
1654static const unsigned int audio_clkout1_a_pins[] = {
1655 /* CLKOUT1 */
1656 RCAR_GP_PIN(5, 15),
1657};
1658static const unsigned int audio_clkout1_a_mux[] = {
1659 AUDIO_CLKOUT1_A_MARK,
1660};
1661static const unsigned int audio_clkout1_b_pins[] = {
1662 /* CLKOUT1 */
1663 RCAR_GP_PIN(6, 29),
1664};
1665static const unsigned int audio_clkout1_b_mux[] = {
1666 AUDIO_CLKOUT1_B_MARK,
1667};
1668static const unsigned int audio_clkout2_a_pins[] = {
1669 /* CLKOUT2 */
1670 RCAR_GP_PIN(5, 16),
1671};
1672static const unsigned int audio_clkout2_a_mux[] = {
1673 AUDIO_CLKOUT2_A_MARK,
1674};
1675static const unsigned int audio_clkout2_b_pins[] = {
1676 /* CLKOUT2 */
1677 RCAR_GP_PIN(6, 30),
1678};
1679static const unsigned int audio_clkout2_b_mux[] = {
1680 AUDIO_CLKOUT2_B_MARK,
1681};
1682static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1697/* - EtherAVB --------------------------------------------------------------- */
1698static const unsigned int avb_link_pins[] = {
1699 /* AVB_LINK */
1700 RCAR_GP_PIN(2, 12),
1701};
1702static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704};
1705static const unsigned int avb_magic_pins[] = {
1706 /* AVB_MAGIC_ */
1707 RCAR_GP_PIN(2, 10),
1708};
1709static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711};
1712static const unsigned int avb_phy_int_pins[] = {
1713 /* AVB_PHY_INT */
1714 RCAR_GP_PIN(2, 11),
1715};
1716static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1719static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1720 /* AVB_MDC, AVB_MDIO */
1721 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1722};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1723static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725};
1726static const unsigned int avb_mii_pins[] = {
1727 /*
1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1729 * AVB_TD1, AVB_TD2, AVB_TD3,
1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1731 * AVB_RD1, AVB_RD2, AVB_RD3,
1732 * AVB_TXCREFCLK
1733 */
1734 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1735 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1736 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1737 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1738 PIN_NUMBER('A', 12),
1739
1740};
1741static const unsigned int avb_mii_mux[] = {
1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 AVB_TXCREFCLK_MARK,
1747};
1748static const unsigned int avb_avtp_pps_pins[] = {
1749 /* AVB_AVTP_PPS */
1750 RCAR_GP_PIN(2, 6),
1751};
1752static const unsigned int avb_avtp_pps_mux[] = {
1753 AVB_AVTP_PPS_MARK,
1754};
1755static const unsigned int avb_avtp_match_a_pins[] = {
1756 /* AVB_AVTP_MATCH_A */
1757 RCAR_GP_PIN(2, 13),
1758};
1759static const unsigned int avb_avtp_match_a_mux[] = {
1760 AVB_AVTP_MATCH_A_MARK,
1761};
1762static const unsigned int avb_avtp_capture_a_pins[] = {
1763 /* AVB_AVTP_CAPTURE_A */
1764 RCAR_GP_PIN(2, 14),
1765};
1766static const unsigned int avb_avtp_capture_a_mux[] = {
1767 AVB_AVTP_CAPTURE_A_MARK,
1768};
1769static const unsigned int avb_avtp_match_b_pins[] = {
1770 /* AVB_AVTP_MATCH_B */
1771 RCAR_GP_PIN(1, 8),
1772};
1773static const unsigned int avb_avtp_match_b_mux[] = {
1774 AVB_AVTP_MATCH_B_MARK,
1775};
1776static const unsigned int avb_avtp_capture_b_pins[] = {
1777 /* AVB_AVTP_CAPTURE_B */
1778 RCAR_GP_PIN(1, 11),
1779};
1780static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK,
1782};
1783
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1784/* - CAN ------------------------------------------------------------------ */
1785static const unsigned int can0_data_a_pins[] = {
1786 /* TX, RX */
1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1788};
1789static const unsigned int can0_data_a_mux[] = {
1790 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1791};
1792static const unsigned int can0_data_b_pins[] = {
1793 /* TX, RX */
1794 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1795};
1796static const unsigned int can0_data_b_mux[] = {
1797 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1798};
1799static const unsigned int can1_data_pins[] = {
1800 /* TX, RX */
1801 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1802};
1803static const unsigned int can1_data_mux[] = {
1804 CAN1_TX_MARK, CAN1_RX_MARK,
1805};
1806
1807/* - CAN Clock -------------------------------------------------------------- */
1808static const unsigned int can_clk_pins[] = {
1809 /* CLK */
1810 RCAR_GP_PIN(1, 25),
1811};
1812static const unsigned int can_clk_mux[] = {
1813 CAN_CLK_MARK,
1814};
1815
1816/* - CAN FD --------------------------------------------------------------- */
1817static const unsigned int canfd0_data_a_pins[] = {
1818 /* TX, RX */
1819 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1820};
1821static const unsigned int canfd0_data_a_mux[] = {
1822 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1823};
1824static const unsigned int canfd0_data_b_pins[] = {
1825 /* TX, RX */
1826 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1827};
1828static const unsigned int canfd0_data_b_mux[] = {
1829 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1830};
1831static const unsigned int canfd1_data_pins[] = {
1832 /* TX, RX */
1833 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1834};
1835static const unsigned int canfd1_data_mux[] = {
1836 CANFD1_TX_MARK, CANFD1_RX_MARK,
1837};
1838
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]1839#ifdef CONFIG_PINCTRL_PFC_R8A7795
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1840/* - DRIF0 --------------------------------------------------------------- */
1841static const unsigned int drif0_ctrl_a_pins[] = {
1842 /* CLK, SYNC */
1843 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1844};
1845static const unsigned int drif0_ctrl_a_mux[] = {
1846 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1847};
1848static const unsigned int drif0_data0_a_pins[] = {
1849 /* D0 */
1850 RCAR_GP_PIN(6, 10),
1851};
1852static const unsigned int drif0_data0_a_mux[] = {
1853 RIF0_D0_A_MARK,
1854};
1855static const unsigned int drif0_data1_a_pins[] = {
1856 /* D1 */
1857 RCAR_GP_PIN(6, 7),
1858};
1859static const unsigned int drif0_data1_a_mux[] = {
1860 RIF0_D1_A_MARK,
1861};
1862static const unsigned int drif0_ctrl_b_pins[] = {
1863 /* CLK, SYNC */
1864 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1865};
1866static const unsigned int drif0_ctrl_b_mux[] = {
1867 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1868};
1869static const unsigned int drif0_data0_b_pins[] = {
1870 /* D0 */
1871 RCAR_GP_PIN(5, 1),
1872};
1873static const unsigned int drif0_data0_b_mux[] = {
1874 RIF0_D0_B_MARK,
1875};
1876static const unsigned int drif0_data1_b_pins[] = {
1877 /* D1 */
1878 RCAR_GP_PIN(5, 2),
1879};
1880static const unsigned int drif0_data1_b_mux[] = {
1881 RIF0_D1_B_MARK,
1882};
1883static const unsigned int drif0_ctrl_c_pins[] = {
1884 /* CLK, SYNC */
1885 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1886};
1887static const unsigned int drif0_ctrl_c_mux[] = {
1888 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1889};
1890static const unsigned int drif0_data0_c_pins[] = {
1891 /* D0 */
1892 RCAR_GP_PIN(5, 13),
1893};
1894static const unsigned int drif0_data0_c_mux[] = {
1895 RIF0_D0_C_MARK,
1896};
1897static const unsigned int drif0_data1_c_pins[] = {
1898 /* D1 */
1899 RCAR_GP_PIN(5, 14),
1900};
1901static const unsigned int drif0_data1_c_mux[] = {
1902 RIF0_D1_C_MARK,
1903};
1904/* - DRIF1 --------------------------------------------------------------- */
1905static const unsigned int drif1_ctrl_a_pins[] = {
1906 /* CLK, SYNC */
1907 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1908};
1909static const unsigned int drif1_ctrl_a_mux[] = {
1910 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1911};
1912static const unsigned int drif1_data0_a_pins[] = {
1913 /* D0 */
1914 RCAR_GP_PIN(6, 19),
1915};
1916static const unsigned int drif1_data0_a_mux[] = {
1917 RIF1_D0_A_MARK,
1918};
1919static const unsigned int drif1_data1_a_pins[] = {
1920 /* D1 */
1921 RCAR_GP_PIN(6, 20),
1922};
1923static const unsigned int drif1_data1_a_mux[] = {
1924 RIF1_D1_A_MARK,
1925};
1926static const unsigned int drif1_ctrl_b_pins[] = {
1927 /* CLK, SYNC */
1928 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1929};
1930static const unsigned int drif1_ctrl_b_mux[] = {
1931 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1932};
1933static const unsigned int drif1_data0_b_pins[] = {
1934 /* D0 */
1935 RCAR_GP_PIN(5, 7),
1936};
1937static const unsigned int drif1_data0_b_mux[] = {
1938 RIF1_D0_B_MARK,
1939};
1940static const unsigned int drif1_data1_b_pins[] = {
1941 /* D1 */
1942 RCAR_GP_PIN(5, 8),
1943};
1944static const unsigned int drif1_data1_b_mux[] = {
1945 RIF1_D1_B_MARK,
1946};
1947static const unsigned int drif1_ctrl_c_pins[] = {
1948 /* CLK, SYNC */
1949 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1950};
1951static const unsigned int drif1_ctrl_c_mux[] = {
1952 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1953};
1954static const unsigned int drif1_data0_c_pins[] = {
1955 /* D0 */
1956 RCAR_GP_PIN(5, 6),
1957};
1958static const unsigned int drif1_data0_c_mux[] = {
1959 RIF1_D0_C_MARK,
1960};
1961static const unsigned int drif1_data1_c_pins[] = {
1962 /* D1 */
1963 RCAR_GP_PIN(5, 10),
1964};
1965static const unsigned int drif1_data1_c_mux[] = {
1966 RIF1_D1_C_MARK,
1967};
1968/* - DRIF2 --------------------------------------------------------------- */
1969static const unsigned int drif2_ctrl_a_pins[] = {
1970 /* CLK, SYNC */
1971 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1972};
1973static const unsigned int drif2_ctrl_a_mux[] = {
1974 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1975};
1976static const unsigned int drif2_data0_a_pins[] = {
1977 /* D0 */
1978 RCAR_GP_PIN(6, 7),
1979};
1980static const unsigned int drif2_data0_a_mux[] = {
1981 RIF2_D0_A_MARK,
1982};
1983static const unsigned int drif2_data1_a_pins[] = {
1984 /* D1 */
1985 RCAR_GP_PIN(6, 10),
1986};
1987static const unsigned int drif2_data1_a_mux[] = {
1988 RIF2_D1_A_MARK,
1989};
1990static const unsigned int drif2_ctrl_b_pins[] = {
1991 /* CLK, SYNC */
1992 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1993};
1994static const unsigned int drif2_ctrl_b_mux[] = {
1995 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1996};
1997static const unsigned int drif2_data0_b_pins[] = {
1998 /* D0 */
1999 RCAR_GP_PIN(6, 30),
2000};
2001static const unsigned int drif2_data0_b_mux[] = {
2002 RIF2_D0_B_MARK,
2003};
2004static const unsigned int drif2_data1_b_pins[] = {
2005 /* D1 */
2006 RCAR_GP_PIN(6, 31),
2007};
2008static const unsigned int drif2_data1_b_mux[] = {
2009 RIF2_D1_B_MARK,
2010};
2011/* - DRIF3 --------------------------------------------------------------- */
2012static const unsigned int drif3_ctrl_a_pins[] = {
2013 /* CLK, SYNC */
2014 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2015};
2016static const unsigned int drif3_ctrl_a_mux[] = {
2017 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2018};
2019static const unsigned int drif3_data0_a_pins[] = {
2020 /* D0 */
2021 RCAR_GP_PIN(6, 19),
2022};
2023static const unsigned int drif3_data0_a_mux[] = {
2024 RIF3_D0_A_MARK,
2025};
2026static const unsigned int drif3_data1_a_pins[] = {
2027 /* D1 */
2028 RCAR_GP_PIN(6, 20),
2029};
2030static const unsigned int drif3_data1_a_mux[] = {
2031 RIF3_D1_A_MARK,
2032};
2033static const unsigned int drif3_ctrl_b_pins[] = {
2034 /* CLK, SYNC */
2035 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2036};
2037static const unsigned int drif3_ctrl_b_mux[] = {
2038 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2039};
2040static const unsigned int drif3_data0_b_pins[] = {
2041 /* D0 */
2042 RCAR_GP_PIN(6, 28),
2043};
2044static const unsigned int drif3_data0_b_mux[] = {
2045 RIF3_D0_B_MARK,
2046};
2047static const unsigned int drif3_data1_b_pins[] = {
2048 /* D1 */
2049 RCAR_GP_PIN(6, 29),
2050};
2051static const unsigned int drif3_data1_b_mux[] = {
2052 RIF3_D1_B_MARK,
2053};
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]2054#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2055
2056/* - DU --------------------------------------------------------------------- */
2057static const unsigned int du_rgb666_pins[] = {
2058 /* R[7:2], G[7:2], B[7:2] */
2059 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2060 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2061 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2062 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2063 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2064 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2065};
2066static const unsigned int du_rgb666_mux[] = {
2067 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2068 DU_DR3_MARK, DU_DR2_MARK,
2069 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2070 DU_DG3_MARK, DU_DG2_MARK,
2071 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2072 DU_DB3_MARK, DU_DB2_MARK,
2073};
2074static const unsigned int du_rgb888_pins[] = {
2075 /* R[7:0], G[7:0], B[7:0] */
2076 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2077 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2078 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2079 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2080 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2081 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2082 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2083 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2084 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2085};
2086static const unsigned int du_rgb888_mux[] = {
2087 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2088 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2089 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2090 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2091 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2092 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2093};
2094static const unsigned int du_clk_out_0_pins[] = {
2095 /* CLKOUT */
2096 RCAR_GP_PIN(1, 27),
2097};
2098static const unsigned int du_clk_out_0_mux[] = {
2099 DU_DOTCLKOUT0_MARK
2100};
2101static const unsigned int du_clk_out_1_pins[] = {
2102 /* CLKOUT */
2103 RCAR_GP_PIN(2, 3),
2104};
2105static const unsigned int du_clk_out_1_mux[] = {
2106 DU_DOTCLKOUT1_MARK
2107};
2108static const unsigned int du_sync_pins[] = {
2109 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2110 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2111};
2112static const unsigned int du_sync_mux[] = {
2113 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2114};
2115static const unsigned int du_oddf_pins[] = {
2116 /* EXDISP/EXODDF/EXCDE */
2117 RCAR_GP_PIN(2, 2),
2118};
2119static const unsigned int du_oddf_mux[] = {
2120 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2121};
2122static const unsigned int du_cde_pins[] = {
2123 /* CDE */
2124 RCAR_GP_PIN(2, 0),
2125};
2126static const unsigned int du_cde_mux[] = {
2127 DU_CDE_MARK,
2128};
2129static const unsigned int du_disp_pins[] = {
2130 /* DISP */
2131 RCAR_GP_PIN(2, 1),
2132};
2133static const unsigned int du_disp_mux[] = {
2134 DU_DISP_MARK,
2135};
2136
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2137/* - HSCIF0 ----------------------------------------------------------------- */
2138static const unsigned int hscif0_data_pins[] = {
2139 /* RX, TX */
2140 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2141};
2142static const unsigned int hscif0_data_mux[] = {
2143 HRX0_MARK, HTX0_MARK,
2144};
2145static const unsigned int hscif0_clk_pins[] = {
2146 /* SCK */
2147 RCAR_GP_PIN(5, 12),
2148};
2149static const unsigned int hscif0_clk_mux[] = {
2150 HSCK0_MARK,
2151};
2152static const unsigned int hscif0_ctrl_pins[] = {
2153 /* RTS, CTS */
2154 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2155};
2156static const unsigned int hscif0_ctrl_mux[] = {
2157 HRTS0_N_MARK, HCTS0_N_MARK,
2158};
2159/* - HSCIF1 ----------------------------------------------------------------- */
2160static const unsigned int hscif1_data_a_pins[] = {
2161 /* RX, TX */
2162 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2163};
2164static const unsigned int hscif1_data_a_mux[] = {
2165 HRX1_A_MARK, HTX1_A_MARK,
2166};
2167static const unsigned int hscif1_clk_a_pins[] = {
2168 /* SCK */
2169 RCAR_GP_PIN(6, 21),
2170};
2171static const unsigned int hscif1_clk_a_mux[] = {
2172 HSCK1_A_MARK,
2173};
2174static const unsigned int hscif1_ctrl_a_pins[] = {
2175 /* RTS, CTS */
2176 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2177};
2178static const unsigned int hscif1_ctrl_a_mux[] = {
2179 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2180};
2181
2182static const unsigned int hscif1_data_b_pins[] = {
2183 /* RX, TX */
2184 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2185};
2186static const unsigned int hscif1_data_b_mux[] = {
2187 HRX1_B_MARK, HTX1_B_MARK,
2188};
2189static const unsigned int hscif1_clk_b_pins[] = {
2190 /* SCK */
2191 RCAR_GP_PIN(5, 0),
2192};
2193static const unsigned int hscif1_clk_b_mux[] = {
2194 HSCK1_B_MARK,
2195};
2196static const unsigned int hscif1_ctrl_b_pins[] = {
2197 /* RTS, CTS */
2198 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2199};
2200static const unsigned int hscif1_ctrl_b_mux[] = {
2201 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2202};
2203/* - HSCIF2 ----------------------------------------------------------------- */
2204static const unsigned int hscif2_data_a_pins[] = {
2205 /* RX, TX */
2206 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2207};
2208static const unsigned int hscif2_data_a_mux[] = {
2209 HRX2_A_MARK, HTX2_A_MARK,
2210};
2211static const unsigned int hscif2_clk_a_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(6, 10),
2214};
2215static const unsigned int hscif2_clk_a_mux[] = {
2216 HSCK2_A_MARK,
2217};
2218static const unsigned int hscif2_ctrl_a_pins[] = {
2219 /* RTS, CTS */
2220 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2221};
2222static const unsigned int hscif2_ctrl_a_mux[] = {
2223 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2224};
2225
2226static const unsigned int hscif2_data_b_pins[] = {
2227 /* RX, TX */
2228 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2229};
2230static const unsigned int hscif2_data_b_mux[] = {
2231 HRX2_B_MARK, HTX2_B_MARK,
2232};
2233static const unsigned int hscif2_clk_b_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(6, 21),
2236};
2237static const unsigned int hscif2_clk_b_mux[] = {
2238 HSCK2_B_MARK,
2239};
2240static const unsigned int hscif2_ctrl_b_pins[] = {
2241 /* RTS, CTS */
2242 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2243};
2244static const unsigned int hscif2_ctrl_b_mux[] = {
2245 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2246};
2247
2248static const unsigned int hscif2_data_c_pins[] = {
2249 /* RX, TX */
2250 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2251};
2252static const unsigned int hscif2_data_c_mux[] = {
2253 HRX2_C_MARK, HTX2_C_MARK,
2254};
2255static const unsigned int hscif2_clk_c_pins[] = {
2256 /* SCK */
2257 RCAR_GP_PIN(6, 24),
2258};
2259static const unsigned int hscif2_clk_c_mux[] = {
2260 HSCK2_C_MARK,
2261};
2262static const unsigned int hscif2_ctrl_c_pins[] = {
2263 /* RTS, CTS */
2264 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2265};
2266static const unsigned int hscif2_ctrl_c_mux[] = {
2267 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2268};
2269/* - HSCIF3 ----------------------------------------------------------------- */
2270static const unsigned int hscif3_data_a_pins[] = {
2271 /* RX, TX */
2272 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2273};
2274static const unsigned int hscif3_data_a_mux[] = {
2275 HRX3_A_MARK, HTX3_A_MARK,
2276};
2277static const unsigned int hscif3_clk_pins[] = {
2278 /* SCK */
2279 RCAR_GP_PIN(1, 22),
2280};
2281static const unsigned int hscif3_clk_mux[] = {
2282 HSCK3_MARK,
2283};
2284static const unsigned int hscif3_ctrl_pins[] = {
2285 /* RTS, CTS */
2286 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2287};
2288static const unsigned int hscif3_ctrl_mux[] = {
2289 HRTS3_N_MARK, HCTS3_N_MARK,
2290};
2291
2292static const unsigned int hscif3_data_b_pins[] = {
2293 /* RX, TX */
2294 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2295};
2296static const unsigned int hscif3_data_b_mux[] = {
2297 HRX3_B_MARK, HTX3_B_MARK,
2298};
2299static const unsigned int hscif3_data_c_pins[] = {
2300 /* RX, TX */
2301 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2302};
2303static const unsigned int hscif3_data_c_mux[] = {
2304 HRX3_C_MARK, HTX3_C_MARK,
2305};
2306static const unsigned int hscif3_data_d_pins[] = {
2307 /* RX, TX */
2308 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2309};
2310static const unsigned int hscif3_data_d_mux[] = {
2311 HRX3_D_MARK, HTX3_D_MARK,
2312};
2313/* - HSCIF4 ----------------------------------------------------------------- */
2314static const unsigned int hscif4_data_a_pins[] = {
2315 /* RX, TX */
2316 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2317};
2318static const unsigned int hscif4_data_a_mux[] = {
2319 HRX4_A_MARK, HTX4_A_MARK,
2320};
2321static const unsigned int hscif4_clk_pins[] = {
2322 /* SCK */
2323 RCAR_GP_PIN(1, 11),
2324};
2325static const unsigned int hscif4_clk_mux[] = {
2326 HSCK4_MARK,
2327};
2328static const unsigned int hscif4_ctrl_pins[] = {
2329 /* RTS, CTS */
2330 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2331};
2332static const unsigned int hscif4_ctrl_mux[] = {
2333 HRTS4_N_MARK, HCTS4_N_MARK,
2334};
2335
2336static const unsigned int hscif4_data_b_pins[] = {
2337 /* RX, TX */
2338 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2339};
2340static const unsigned int hscif4_data_b_mux[] = {
2341 HRX4_B_MARK, HTX4_B_MARK,
2342};
2343
2344/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2345static const unsigned int i2c0_pins[] = {
2346 /* SCL, SDA */
2347 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2348};
2349
2350static const unsigned int i2c0_mux[] = {
2351 SCL0_MARK, SDA0_MARK,
2352};
2353
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2354static const unsigned int i2c1_a_pins[] = {
2355 /* SDA, SCL */
2356 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2357};
2358static const unsigned int i2c1_a_mux[] = {
2359 SDA1_A_MARK, SCL1_A_MARK,
2360};
2361static const unsigned int i2c1_b_pins[] = {
2362 /* SDA, SCL */
2363 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2364};
2365static const unsigned int i2c1_b_mux[] = {
2366 SDA1_B_MARK, SCL1_B_MARK,
2367};
2368static const unsigned int i2c2_a_pins[] = {
2369 /* SDA, SCL */
2370 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2371};
2372static const unsigned int i2c2_a_mux[] = {
2373 SDA2_A_MARK, SCL2_A_MARK,
2374};
2375static const unsigned int i2c2_b_pins[] = {
2376 /* SDA, SCL */
2377 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2378};
2379static const unsigned int i2c2_b_mux[] = {
2380 SDA2_B_MARK, SCL2_B_MARK,
2381};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2382
2383static const unsigned int i2c3_pins[] = {
2384 /* SCL, SDA */
2385 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2386};
2387
2388static const unsigned int i2c3_mux[] = {
2389 SCL3_MARK, SDA3_MARK,
2390};
2391
2392static const unsigned int i2c5_pins[] = {
2393 /* SCL, SDA */
2394 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2395};
2396
2397static const unsigned int i2c5_mux[] = {
2398 SCL5_MARK, SDA5_MARK,
2399};
2400
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2401static const unsigned int i2c6_a_pins[] = {
2402 /* SDA, SCL */
2403 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2404};
2405static const unsigned int i2c6_a_mux[] = {
2406 SDA6_A_MARK, SCL6_A_MARK,
2407};
2408static const unsigned int i2c6_b_pins[] = {
2409 /* SDA, SCL */
2410 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2411};
2412static const unsigned int i2c6_b_mux[] = {
2413 SDA6_B_MARK, SCL6_B_MARK,
2414};
2415static const unsigned int i2c6_c_pins[] = {
2416 /* SDA, SCL */
2417 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2418};
2419static const unsigned int i2c6_c_mux[] = {
2420 SDA6_C_MARK, SCL6_C_MARK,
2421};
2422
2423/* - INTC-EX ---------------------------------------------------------------- */
2424static const unsigned int intc_ex_irq0_pins[] = {
2425 /* IRQ0 */
2426 RCAR_GP_PIN(2, 0),
2427};
2428static const unsigned int intc_ex_irq0_mux[] = {
2429 IRQ0_MARK,
2430};
2431static const unsigned int intc_ex_irq1_pins[] = {
2432 /* IRQ1 */
2433 RCAR_GP_PIN(2, 1),
2434};
2435static const unsigned int intc_ex_irq1_mux[] = {
2436 IRQ1_MARK,
2437};
2438static const unsigned int intc_ex_irq2_pins[] = {
2439 /* IRQ2 */
2440 RCAR_GP_PIN(2, 2),
2441};
2442static const unsigned int intc_ex_irq2_mux[] = {
2443 IRQ2_MARK,
2444};
2445static const unsigned int intc_ex_irq3_pins[] = {
2446 /* IRQ3 */
2447 RCAR_GP_PIN(2, 3),
2448};
2449static const unsigned int intc_ex_irq3_mux[] = {
2450 IRQ3_MARK,
2451};
2452static const unsigned int intc_ex_irq4_pins[] = {
2453 /* IRQ4 */
2454 RCAR_GP_PIN(2, 4),
2455};
2456static const unsigned int intc_ex_irq4_mux[] = {
2457 IRQ4_MARK,
2458};
2459static const unsigned int intc_ex_irq5_pins[] = {
2460 /* IRQ5 */
2461 RCAR_GP_PIN(2, 5),
2462};
2463static const unsigned int intc_ex_irq5_mux[] = {
2464 IRQ5_MARK,
2465};
2466
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2467/* - MSIOF0 ----------------------------------------------------------------- */
2468static const unsigned int msiof0_clk_pins[] = {
2469 /* SCK */
2470 RCAR_GP_PIN(5, 17),
2471};
2472static const unsigned int msiof0_clk_mux[] = {
2473 MSIOF0_SCK_MARK,
2474};
2475static const unsigned int msiof0_sync_pins[] = {
2476 /* SYNC */
2477 RCAR_GP_PIN(5, 18),
2478};
2479static const unsigned int msiof0_sync_mux[] = {
2480 MSIOF0_SYNC_MARK,
2481};
2482static const unsigned int msiof0_ss1_pins[] = {
2483 /* SS1 */
2484 RCAR_GP_PIN(5, 19),
2485};
2486static const unsigned int msiof0_ss1_mux[] = {
2487 MSIOF0_SS1_MARK,
2488};
2489static const unsigned int msiof0_ss2_pins[] = {
2490 /* SS2 */
2491 RCAR_GP_PIN(5, 21),
2492};
2493static const unsigned int msiof0_ss2_mux[] = {
2494 MSIOF0_SS2_MARK,
2495};
2496static const unsigned int msiof0_txd_pins[] = {
2497 /* TXD */
2498 RCAR_GP_PIN(5, 20),
2499};
2500static const unsigned int msiof0_txd_mux[] = {
2501 MSIOF0_TXD_MARK,
2502};
2503static const unsigned int msiof0_rxd_pins[] = {
2504 /* RXD */
2505 RCAR_GP_PIN(5, 22),
2506};
2507static const unsigned int msiof0_rxd_mux[] = {
2508 MSIOF0_RXD_MARK,
2509};
2510/* - MSIOF1 ----------------------------------------------------------------- */
2511static const unsigned int msiof1_clk_a_pins[] = {
2512 /* SCK */
2513 RCAR_GP_PIN(6, 8),
2514};
2515static const unsigned int msiof1_clk_a_mux[] = {
2516 MSIOF1_SCK_A_MARK,
2517};
2518static const unsigned int msiof1_sync_a_pins[] = {
2519 /* SYNC */
2520 RCAR_GP_PIN(6, 9),
2521};
2522static const unsigned int msiof1_sync_a_mux[] = {
2523 MSIOF1_SYNC_A_MARK,
2524};
2525static const unsigned int msiof1_ss1_a_pins[] = {
2526 /* SS1 */
2527 RCAR_GP_PIN(6, 5),
2528};
2529static const unsigned int msiof1_ss1_a_mux[] = {
2530 MSIOF1_SS1_A_MARK,
2531};
2532static const unsigned int msiof1_ss2_a_pins[] = {
2533 /* SS2 */
2534 RCAR_GP_PIN(6, 6),
2535};
2536static const unsigned int msiof1_ss2_a_mux[] = {
2537 MSIOF1_SS2_A_MARK,
2538};
2539static const unsigned int msiof1_txd_a_pins[] = {
2540 /* TXD */
2541 RCAR_GP_PIN(6, 7),
2542};
2543static const unsigned int msiof1_txd_a_mux[] = {
2544 MSIOF1_TXD_A_MARK,
2545};
2546static const unsigned int msiof1_rxd_a_pins[] = {
2547 /* RXD */
2548 RCAR_GP_PIN(6, 10),
2549};
2550static const unsigned int msiof1_rxd_a_mux[] = {
2551 MSIOF1_RXD_A_MARK,
2552};
2553static const unsigned int msiof1_clk_b_pins[] = {
2554 /* SCK */
2555 RCAR_GP_PIN(5, 9),
2556};
2557static const unsigned int msiof1_clk_b_mux[] = {
2558 MSIOF1_SCK_B_MARK,
2559};
2560static const unsigned int msiof1_sync_b_pins[] = {
2561 /* SYNC */
2562 RCAR_GP_PIN(5, 3),
2563};
2564static const unsigned int msiof1_sync_b_mux[] = {
2565 MSIOF1_SYNC_B_MARK,
2566};
2567static const unsigned int msiof1_ss1_b_pins[] = {
2568 /* SS1 */
2569 RCAR_GP_PIN(5, 4),
2570};
2571static const unsigned int msiof1_ss1_b_mux[] = {
2572 MSIOF1_SS1_B_MARK,
2573};
2574static const unsigned int msiof1_ss2_b_pins[] = {
2575 /* SS2 */
2576 RCAR_GP_PIN(5, 0),
2577};
2578static const unsigned int msiof1_ss2_b_mux[] = {
2579 MSIOF1_SS2_B_MARK,
2580};
2581static const unsigned int msiof1_txd_b_pins[] = {
2582 /* TXD */
2583 RCAR_GP_PIN(5, 8),
2584};
2585static const unsigned int msiof1_txd_b_mux[] = {
2586 MSIOF1_TXD_B_MARK,
2587};
2588static const unsigned int msiof1_rxd_b_pins[] = {
2589 /* RXD */
2590 RCAR_GP_PIN(5, 7),
2591};
2592static const unsigned int msiof1_rxd_b_mux[] = {
2593 MSIOF1_RXD_B_MARK,
2594};
2595static const unsigned int msiof1_clk_c_pins[] = {
2596 /* SCK */
2597 RCAR_GP_PIN(6, 17),
2598};
2599static const unsigned int msiof1_clk_c_mux[] = {
2600 MSIOF1_SCK_C_MARK,
2601};
2602static const unsigned int msiof1_sync_c_pins[] = {
2603 /* SYNC */
2604 RCAR_GP_PIN(6, 18),
2605};
2606static const unsigned int msiof1_sync_c_mux[] = {
2607 MSIOF1_SYNC_C_MARK,
2608};
2609static const unsigned int msiof1_ss1_c_pins[] = {
2610 /* SS1 */
2611 RCAR_GP_PIN(6, 21),
2612};
2613static const unsigned int msiof1_ss1_c_mux[] = {
2614 MSIOF1_SS1_C_MARK,
2615};
2616static const unsigned int msiof1_ss2_c_pins[] = {
2617 /* SS2 */
2618 RCAR_GP_PIN(6, 27),
2619};
2620static const unsigned int msiof1_ss2_c_mux[] = {
2621 MSIOF1_SS2_C_MARK,
2622};
2623static const unsigned int msiof1_txd_c_pins[] = {
2624 /* TXD */
2625 RCAR_GP_PIN(6, 20),
2626};
2627static const unsigned int msiof1_txd_c_mux[] = {
2628 MSIOF1_TXD_C_MARK,
2629};
2630static const unsigned int msiof1_rxd_c_pins[] = {
2631 /* RXD */
2632 RCAR_GP_PIN(6, 19),
2633};
2634static const unsigned int msiof1_rxd_c_mux[] = {
2635 MSIOF1_RXD_C_MARK,
2636};
2637static const unsigned int msiof1_clk_d_pins[] = {
2638 /* SCK */
2639 RCAR_GP_PIN(5, 12),
2640};
2641static const unsigned int msiof1_clk_d_mux[] = {
2642 MSIOF1_SCK_D_MARK,
2643};
2644static const unsigned int msiof1_sync_d_pins[] = {
2645 /* SYNC */
2646 RCAR_GP_PIN(5, 15),
2647};
2648static const unsigned int msiof1_sync_d_mux[] = {
2649 MSIOF1_SYNC_D_MARK,
2650};
2651static const unsigned int msiof1_ss1_d_pins[] = {
2652 /* SS1 */
2653 RCAR_GP_PIN(5, 16),
2654};
2655static const unsigned int msiof1_ss1_d_mux[] = {
2656 MSIOF1_SS1_D_MARK,
2657};
2658static const unsigned int msiof1_ss2_d_pins[] = {
2659 /* SS2 */
2660 RCAR_GP_PIN(5, 21),
2661};
2662static const unsigned int msiof1_ss2_d_mux[] = {
2663 MSIOF1_SS2_D_MARK,
2664};
2665static const unsigned int msiof1_txd_d_pins[] = {
2666 /* TXD */
2667 RCAR_GP_PIN(5, 14),
2668};
2669static const unsigned int msiof1_txd_d_mux[] = {
2670 MSIOF1_TXD_D_MARK,
2671};
2672static const unsigned int msiof1_rxd_d_pins[] = {
2673 /* RXD */
2674 RCAR_GP_PIN(5, 13),
2675};
2676static const unsigned int msiof1_rxd_d_mux[] = {
2677 MSIOF1_RXD_D_MARK,
2678};
2679static const unsigned int msiof1_clk_e_pins[] = {
2680 /* SCK */
2681 RCAR_GP_PIN(3, 0),
2682};
2683static const unsigned int msiof1_clk_e_mux[] = {
2684 MSIOF1_SCK_E_MARK,
2685};
2686static const unsigned int msiof1_sync_e_pins[] = {
2687 /* SYNC */
2688 RCAR_GP_PIN(3, 1),
2689};
2690static const unsigned int msiof1_sync_e_mux[] = {
2691 MSIOF1_SYNC_E_MARK,
2692};
2693static const unsigned int msiof1_ss1_e_pins[] = {
2694 /* SS1 */
2695 RCAR_GP_PIN(3, 4),
2696};
2697static const unsigned int msiof1_ss1_e_mux[] = {
2698 MSIOF1_SS1_E_MARK,
2699};
2700static const unsigned int msiof1_ss2_e_pins[] = {
2701 /* SS2 */
2702 RCAR_GP_PIN(3, 5),
2703};
2704static const unsigned int msiof1_ss2_e_mux[] = {
2705 MSIOF1_SS2_E_MARK,
2706};
2707static const unsigned int msiof1_txd_e_pins[] = {
2708 /* TXD */
2709 RCAR_GP_PIN(3, 3),
2710};
2711static const unsigned int msiof1_txd_e_mux[] = {
2712 MSIOF1_TXD_E_MARK,
2713};
2714static const unsigned int msiof1_rxd_e_pins[] = {
2715 /* RXD */
2716 RCAR_GP_PIN(3, 2),
2717};
2718static const unsigned int msiof1_rxd_e_mux[] = {
2719 MSIOF1_RXD_E_MARK,
2720};
2721static const unsigned int msiof1_clk_f_pins[] = {
2722 /* SCK */
2723 RCAR_GP_PIN(5, 23),
2724};
2725static const unsigned int msiof1_clk_f_mux[] = {
2726 MSIOF1_SCK_F_MARK,
2727};
2728static const unsigned int msiof1_sync_f_pins[] = {
2729 /* SYNC */
2730 RCAR_GP_PIN(5, 24),
2731};
2732static const unsigned int msiof1_sync_f_mux[] = {
2733 MSIOF1_SYNC_F_MARK,
2734};
2735static const unsigned int msiof1_ss1_f_pins[] = {
2736 /* SS1 */
2737 RCAR_GP_PIN(6, 1),
2738};
2739static const unsigned int msiof1_ss1_f_mux[] = {
2740 MSIOF1_SS1_F_MARK,
2741};
2742static const unsigned int msiof1_ss2_f_pins[] = {
2743 /* SS2 */
2744 RCAR_GP_PIN(6, 2),
2745};
2746static const unsigned int msiof1_ss2_f_mux[] = {
2747 MSIOF1_SS2_F_MARK,
2748};
2749static const unsigned int msiof1_txd_f_pins[] = {
2750 /* TXD */
2751 RCAR_GP_PIN(6, 0),
2752};
2753static const unsigned int msiof1_txd_f_mux[] = {
2754 MSIOF1_TXD_F_MARK,
2755};
2756static const unsigned int msiof1_rxd_f_pins[] = {
2757 /* RXD */
2758 RCAR_GP_PIN(5, 25),
2759};
2760static const unsigned int msiof1_rxd_f_mux[] = {
2761 MSIOF1_RXD_F_MARK,
2762};
2763static const unsigned int msiof1_clk_g_pins[] = {
2764 /* SCK */
2765 RCAR_GP_PIN(3, 6),
2766};
2767static const unsigned int msiof1_clk_g_mux[] = {
2768 MSIOF1_SCK_G_MARK,
2769};
2770static const unsigned int msiof1_sync_g_pins[] = {
2771 /* SYNC */
2772 RCAR_GP_PIN(3, 7),
2773};
2774static const unsigned int msiof1_sync_g_mux[] = {
2775 MSIOF1_SYNC_G_MARK,
2776};
2777static const unsigned int msiof1_ss1_g_pins[] = {
2778 /* SS1 */
2779 RCAR_GP_PIN(3, 10),
2780};
2781static const unsigned int msiof1_ss1_g_mux[] = {
2782 MSIOF1_SS1_G_MARK,
2783};
2784static const unsigned int msiof1_ss2_g_pins[] = {
2785 /* SS2 */
2786 RCAR_GP_PIN(3, 11),
2787};
2788static const unsigned int msiof1_ss2_g_mux[] = {
2789 MSIOF1_SS2_G_MARK,
2790};
2791static const unsigned int msiof1_txd_g_pins[] = {
2792 /* TXD */
2793 RCAR_GP_PIN(3, 9),
2794};
2795static const unsigned int msiof1_txd_g_mux[] = {
2796 MSIOF1_TXD_G_MARK,
2797};
2798static const unsigned int msiof1_rxd_g_pins[] = {
2799 /* RXD */
2800 RCAR_GP_PIN(3, 8),
2801};
2802static const unsigned int msiof1_rxd_g_mux[] = {
2803 MSIOF1_RXD_G_MARK,
2804};
2805/* - MSIOF2 ----------------------------------------------------------------- */
2806static const unsigned int msiof2_clk_a_pins[] = {
2807 /* SCK */
2808 RCAR_GP_PIN(1, 9),
2809};
2810static const unsigned int msiof2_clk_a_mux[] = {
2811 MSIOF2_SCK_A_MARK,
2812};
2813static const unsigned int msiof2_sync_a_pins[] = {
2814 /* SYNC */
2815 RCAR_GP_PIN(1, 8),
2816};
2817static const unsigned int msiof2_sync_a_mux[] = {
2818 MSIOF2_SYNC_A_MARK,
2819};
2820static const unsigned int msiof2_ss1_a_pins[] = {
2821 /* SS1 */
2822 RCAR_GP_PIN(1, 6),
2823};
2824static const unsigned int msiof2_ss1_a_mux[] = {
2825 MSIOF2_SS1_A_MARK,
2826};
2827static const unsigned int msiof2_ss2_a_pins[] = {
2828 /* SS2 */
2829 RCAR_GP_PIN(1, 7),
2830};
2831static const unsigned int msiof2_ss2_a_mux[] = {
2832 MSIOF2_SS2_A_MARK,
2833};
2834static const unsigned int msiof2_txd_a_pins[] = {
2835 /* TXD */
2836 RCAR_GP_PIN(1, 11),
2837};
2838static const unsigned int msiof2_txd_a_mux[] = {
2839 MSIOF2_TXD_A_MARK,
2840};
2841static const unsigned int msiof2_rxd_a_pins[] = {
2842 /* RXD */
2843 RCAR_GP_PIN(1, 10),
2844};
2845static const unsigned int msiof2_rxd_a_mux[] = {
2846 MSIOF2_RXD_A_MARK,
2847};
2848static const unsigned int msiof2_clk_b_pins[] = {
2849 /* SCK */
2850 RCAR_GP_PIN(0, 4),
2851};
2852static const unsigned int msiof2_clk_b_mux[] = {
2853 MSIOF2_SCK_B_MARK,
2854};
2855static const unsigned int msiof2_sync_b_pins[] = {
2856 /* SYNC */
2857 RCAR_GP_PIN(0, 5),
2858};
2859static const unsigned int msiof2_sync_b_mux[] = {
2860 MSIOF2_SYNC_B_MARK,
2861};
2862static const unsigned int msiof2_ss1_b_pins[] = {
2863 /* SS1 */
2864 RCAR_GP_PIN(0, 0),
2865};
2866static const unsigned int msiof2_ss1_b_mux[] = {
2867 MSIOF2_SS1_B_MARK,
2868};
2869static const unsigned int msiof2_ss2_b_pins[] = {
2870 /* SS2 */
2871 RCAR_GP_PIN(0, 1),
2872};
2873static const unsigned int msiof2_ss2_b_mux[] = {
2874 MSIOF2_SS2_B_MARK,
2875};
2876static const unsigned int msiof2_txd_b_pins[] = {
2877 /* TXD */
2878 RCAR_GP_PIN(0, 7),
2879};
2880static const unsigned int msiof2_txd_b_mux[] = {
2881 MSIOF2_TXD_B_MARK,
2882};
2883static const unsigned int msiof2_rxd_b_pins[] = {
2884 /* RXD */
2885 RCAR_GP_PIN(0, 6),
2886};
2887static const unsigned int msiof2_rxd_b_mux[] = {
2888 MSIOF2_RXD_B_MARK,
2889};
2890static const unsigned int msiof2_clk_c_pins[] = {
2891 /* SCK */
2892 RCAR_GP_PIN(2, 12),
2893};
2894static const unsigned int msiof2_clk_c_mux[] = {
2895 MSIOF2_SCK_C_MARK,
2896};
2897static const unsigned int msiof2_sync_c_pins[] = {
2898 /* SYNC */
2899 RCAR_GP_PIN(2, 11),
2900};
2901static const unsigned int msiof2_sync_c_mux[] = {
2902 MSIOF2_SYNC_C_MARK,
2903};
2904static const unsigned int msiof2_ss1_c_pins[] = {
2905 /* SS1 */
2906 RCAR_GP_PIN(2, 10),
2907};
2908static const unsigned int msiof2_ss1_c_mux[] = {
2909 MSIOF2_SS1_C_MARK,
2910};
2911static const unsigned int msiof2_ss2_c_pins[] = {
2912 /* SS2 */
2913 RCAR_GP_PIN(2, 9),
2914};
2915static const unsigned int msiof2_ss2_c_mux[] = {
2916 MSIOF2_SS2_C_MARK,
2917};
2918static const unsigned int msiof2_txd_c_pins[] = {
2919 /* TXD */
2920 RCAR_GP_PIN(2, 14),
2921};
2922static const unsigned int msiof2_txd_c_mux[] = {
2923 MSIOF2_TXD_C_MARK,
2924};
2925static const unsigned int msiof2_rxd_c_pins[] = {
2926 /* RXD */
2927 RCAR_GP_PIN(2, 13),
2928};
2929static const unsigned int msiof2_rxd_c_mux[] = {
2930 MSIOF2_RXD_C_MARK,
2931};
2932static const unsigned int msiof2_clk_d_pins[] = {
2933 /* SCK */
2934 RCAR_GP_PIN(0, 8),
2935};
2936static const unsigned int msiof2_clk_d_mux[] = {
2937 MSIOF2_SCK_D_MARK,
2938};
2939static const unsigned int msiof2_sync_d_pins[] = {
2940 /* SYNC */
2941 RCAR_GP_PIN(0, 9),
2942};
2943static const unsigned int msiof2_sync_d_mux[] = {
2944 MSIOF2_SYNC_D_MARK,
2945};
2946static const unsigned int msiof2_ss1_d_pins[] = {
2947 /* SS1 */
2948 RCAR_GP_PIN(0, 12),
2949};
2950static const unsigned int msiof2_ss1_d_mux[] = {
2951 MSIOF2_SS1_D_MARK,
2952};
2953static const unsigned int msiof2_ss2_d_pins[] = {
2954 /* SS2 */
2955 RCAR_GP_PIN(0, 13),
2956};
2957static const unsigned int msiof2_ss2_d_mux[] = {
2958 MSIOF2_SS2_D_MARK,
2959};
2960static const unsigned int msiof2_txd_d_pins[] = {
2961 /* TXD */
2962 RCAR_GP_PIN(0, 11),
2963};
2964static const unsigned int msiof2_txd_d_mux[] = {
2965 MSIOF2_TXD_D_MARK,
2966};
2967static const unsigned int msiof2_rxd_d_pins[] = {
2968 /* RXD */
2969 RCAR_GP_PIN(0, 10),
2970};
2971static const unsigned int msiof2_rxd_d_mux[] = {
2972 MSIOF2_RXD_D_MARK,
2973};
2974/* - MSIOF3 ----------------------------------------------------------------- */
2975static const unsigned int msiof3_clk_a_pins[] = {
2976 /* SCK */
2977 RCAR_GP_PIN(0, 0),
2978};
2979static const unsigned int msiof3_clk_a_mux[] = {
2980 MSIOF3_SCK_A_MARK,
2981};
2982static const unsigned int msiof3_sync_a_pins[] = {
2983 /* SYNC */
2984 RCAR_GP_PIN(0, 1),
2985};
2986static const unsigned int msiof3_sync_a_mux[] = {
2987 MSIOF3_SYNC_A_MARK,
2988};
2989static const unsigned int msiof3_ss1_a_pins[] = {
2990 /* SS1 */
2991 RCAR_GP_PIN(0, 14),
2992};
2993static const unsigned int msiof3_ss1_a_mux[] = {
2994 MSIOF3_SS1_A_MARK,
2995};
2996static const unsigned int msiof3_ss2_a_pins[] = {
2997 /* SS2 */
2998 RCAR_GP_PIN(0, 15),
2999};
3000static const unsigned int msiof3_ss2_a_mux[] = {
3001 MSIOF3_SS2_A_MARK,
3002};
3003static const unsigned int msiof3_txd_a_pins[] = {
3004 /* TXD */
3005 RCAR_GP_PIN(0, 3),
3006};
3007static const unsigned int msiof3_txd_a_mux[] = {
3008 MSIOF3_TXD_A_MARK,
3009};
3010static const unsigned int msiof3_rxd_a_pins[] = {
3011 /* RXD */
3012 RCAR_GP_PIN(0, 2),
3013};
3014static const unsigned int msiof3_rxd_a_mux[] = {
3015 MSIOF3_RXD_A_MARK,
3016};
3017static const unsigned int msiof3_clk_b_pins[] = {
3018 /* SCK */
3019 RCAR_GP_PIN(1, 2),
3020};
3021static const unsigned int msiof3_clk_b_mux[] = {
3022 MSIOF3_SCK_B_MARK,
3023};
3024static const unsigned int msiof3_sync_b_pins[] = {
3025 /* SYNC */
3026 RCAR_GP_PIN(1, 0),
3027};
3028static const unsigned int msiof3_sync_b_mux[] = {
3029 MSIOF3_SYNC_B_MARK,
3030};
3031static const unsigned int msiof3_ss1_b_pins[] = {
3032 /* SS1 */
3033 RCAR_GP_PIN(1, 4),
3034};
3035static const unsigned int msiof3_ss1_b_mux[] = {
3036 MSIOF3_SS1_B_MARK,
3037};
3038static const unsigned int msiof3_ss2_b_pins[] = {
3039 /* SS2 */
3040 RCAR_GP_PIN(1, 5),
3041};
3042static const unsigned int msiof3_ss2_b_mux[] = {
3043 MSIOF3_SS2_B_MARK,
3044};
3045static const unsigned int msiof3_txd_b_pins[] = {
3046 /* TXD */
3047 RCAR_GP_PIN(1, 1),
3048};
3049static const unsigned int msiof3_txd_b_mux[] = {
3050 MSIOF3_TXD_B_MARK,
3051};
3052static const unsigned int msiof3_rxd_b_pins[] = {
3053 /* RXD */
3054 RCAR_GP_PIN(1, 3),
3055};
3056static const unsigned int msiof3_rxd_b_mux[] = {
3057 MSIOF3_RXD_B_MARK,
3058};
3059static const unsigned int msiof3_clk_c_pins[] = {
3060 /* SCK */
3061 RCAR_GP_PIN(1, 12),
3062};
3063static const unsigned int msiof3_clk_c_mux[] = {
3064 MSIOF3_SCK_C_MARK,
3065};
3066static const unsigned int msiof3_sync_c_pins[] = {
3067 /* SYNC */
3068 RCAR_GP_PIN(1, 13),
3069};
3070static const unsigned int msiof3_sync_c_mux[] = {
3071 MSIOF3_SYNC_C_MARK,
3072};
3073static const unsigned int msiof3_txd_c_pins[] = {
3074 /* TXD */
3075 RCAR_GP_PIN(1, 15),
3076};
3077static const unsigned int msiof3_txd_c_mux[] = {
3078 MSIOF3_TXD_C_MARK,
3079};
3080static const unsigned int msiof3_rxd_c_pins[] = {
3081 /* RXD */
3082 RCAR_GP_PIN(1, 14),
3083};
3084static const unsigned int msiof3_rxd_c_mux[] = {
3085 MSIOF3_RXD_C_MARK,
3086};
3087static const unsigned int msiof3_clk_d_pins[] = {
3088 /* SCK */
3089 RCAR_GP_PIN(1, 22),
3090};
3091static const unsigned int msiof3_clk_d_mux[] = {
3092 MSIOF3_SCK_D_MARK,
3093};
3094static const unsigned int msiof3_sync_d_pins[] = {
3095 /* SYNC */
3096 RCAR_GP_PIN(1, 23),
3097};
3098static const unsigned int msiof3_sync_d_mux[] = {
3099 MSIOF3_SYNC_D_MARK,
3100};
3101static const unsigned int msiof3_ss1_d_pins[] = {
3102 /* SS1 */
3103 RCAR_GP_PIN(1, 26),
3104};
3105static const unsigned int msiof3_ss1_d_mux[] = {
3106 MSIOF3_SS1_D_MARK,
3107};
3108static const unsigned int msiof3_txd_d_pins[] = {
3109 /* TXD */
3110 RCAR_GP_PIN(1, 25),
3111};
3112static const unsigned int msiof3_txd_d_mux[] = {
3113 MSIOF3_TXD_D_MARK,
3114};
3115static const unsigned int msiof3_rxd_d_pins[] = {
3116 /* RXD */
3117 RCAR_GP_PIN(1, 24),
3118};
3119static const unsigned int msiof3_rxd_d_mux[] = {
3120 MSIOF3_RXD_D_MARK,
3121};
3122static const unsigned int msiof3_clk_e_pins[] = {
3123 /* SCK */
3124 RCAR_GP_PIN(2, 3),
3125};
3126static const unsigned int msiof3_clk_e_mux[] = {
3127 MSIOF3_SCK_E_MARK,
3128};
3129static const unsigned int msiof3_sync_e_pins[] = {
3130 /* SYNC */
3131 RCAR_GP_PIN(2, 2),
3132};
3133static const unsigned int msiof3_sync_e_mux[] = {
3134 MSIOF3_SYNC_E_MARK,
3135};
3136static const unsigned int msiof3_ss1_e_pins[] = {
3137 /* SS1 */
3138 RCAR_GP_PIN(2, 1),
3139};
3140static const unsigned int msiof3_ss1_e_mux[] = {
3141 MSIOF3_SS1_E_MARK,
3142};
3143static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3144 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3145 RCAR_GP_PIN(2, 0),
3146};
3147static const unsigned int msiof3_ss2_e_mux[] = {
3148 MSIOF3_SS2_E_MARK,
3149};
3150static const unsigned int msiof3_txd_e_pins[] = {
3151 /* TXD */
3152 RCAR_GP_PIN(2, 5),
3153};
3154static const unsigned int msiof3_txd_e_mux[] = {
3155 MSIOF3_TXD_E_MARK,
3156};
3157static const unsigned int msiof3_rxd_e_pins[] = {
3158 /* RXD */
3159 RCAR_GP_PIN(2, 4),
3160};
3161static const unsigned int msiof3_rxd_e_mux[] = {
3162 MSIOF3_RXD_E_MARK,
3163};
3164
3165/* - PWM0 --------------------------------------------------------------------*/
3166static const unsigned int pwm0_pins[] = {
3167 /* PWM */
3168 RCAR_GP_PIN(2, 6),
3169};
3170static const unsigned int pwm0_mux[] = {
3171 PWM0_MARK,
3172};
3173/* - PWM1 --------------------------------------------------------------------*/
3174static const unsigned int pwm1_a_pins[] = {
3175 /* PWM */
3176 RCAR_GP_PIN(2, 7),
3177};
3178static const unsigned int pwm1_a_mux[] = {
3179 PWM1_A_MARK,
3180};
3181static const unsigned int pwm1_b_pins[] = {
3182 /* PWM */
3183 RCAR_GP_PIN(1, 8),
3184};
3185static const unsigned int pwm1_b_mux[] = {
3186 PWM1_B_MARK,
3187};
3188/* - PWM2 --------------------------------------------------------------------*/
3189static const unsigned int pwm2_a_pins[] = {
3190 /* PWM */
3191 RCAR_GP_PIN(2, 8),
3192};
3193static const unsigned int pwm2_a_mux[] = {
3194 PWM2_A_MARK,
3195};
3196static const unsigned int pwm2_b_pins[] = {
3197 /* PWM */
3198 RCAR_GP_PIN(1, 11),
3199};
3200static const unsigned int pwm2_b_mux[] = {
3201 PWM2_B_MARK,
3202};
3203/* - PWM3 --------------------------------------------------------------------*/
3204static const unsigned int pwm3_a_pins[] = {
3205 /* PWM */
3206 RCAR_GP_PIN(1, 0),
3207};
3208static const unsigned int pwm3_a_mux[] = {
3209 PWM3_A_MARK,
3210};
3211static const unsigned int pwm3_b_pins[] = {
3212 /* PWM */
3213 RCAR_GP_PIN(2, 2),
3214};
3215static const unsigned int pwm3_b_mux[] = {
3216 PWM3_B_MARK,
3217};
3218/* - PWM4 --------------------------------------------------------------------*/
3219static const unsigned int pwm4_a_pins[] = {
3220 /* PWM */
3221 RCAR_GP_PIN(1, 1),
3222};
3223static const unsigned int pwm4_a_mux[] = {
3224 PWM4_A_MARK,
3225};
3226static const unsigned int pwm4_b_pins[] = {
3227 /* PWM */
3228 RCAR_GP_PIN(2, 3),
3229};
3230static const unsigned int pwm4_b_mux[] = {
3231 PWM4_B_MARK,
3232};
3233/* - PWM5 --------------------------------------------------------------------*/
3234static const unsigned int pwm5_a_pins[] = {
3235 /* PWM */
3236 RCAR_GP_PIN(1, 2),
3237};
3238static const unsigned int pwm5_a_mux[] = {
3239 PWM5_A_MARK,
3240};
3241static const unsigned int pwm5_b_pins[] = {
3242 /* PWM */
3243 RCAR_GP_PIN(2, 4),
3244};
3245static const unsigned int pwm5_b_mux[] = {
3246 PWM5_B_MARK,
3247};
3248/* - PWM6 --------------------------------------------------------------------*/
3249static const unsigned int pwm6_a_pins[] = {
3250 /* PWM */
3251 RCAR_GP_PIN(1, 3),
3252};
3253static const unsigned int pwm6_a_mux[] = {
3254 PWM6_A_MARK,
3255};
3256static const unsigned int pwm6_b_pins[] = {
3257 /* PWM */
3258 RCAR_GP_PIN(2, 5),
3259};
3260static const unsigned int pwm6_b_mux[] = {
3261 PWM6_B_MARK,
3262};
3263
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3264/* - SATA --------------------------------------------------------------------*/
3265static const unsigned int sata0_devslp_a_pins[] = {
3266 /* DEVSLP */
3267 RCAR_GP_PIN(6, 16),
3268};
3269static const unsigned int sata0_devslp_a_mux[] = {
3270 SATA_DEVSLP_A_MARK,
3271};
3272static const unsigned int sata0_devslp_b_pins[] = {
3273 /* DEVSLP */
3274 RCAR_GP_PIN(4, 6),
3275};
3276static const unsigned int sata0_devslp_b_mux[] = {
3277 SATA_DEVSLP_B_MARK,
3278};
3279
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3280/* - SCIF0 ------------------------------------------------------------------ */
3281static const unsigned int scif0_data_pins[] = {
3282 /* RX, TX */
3283 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3284};
3285static const unsigned int scif0_data_mux[] = {
3286 RX0_MARK, TX0_MARK,
3287};
3288static const unsigned int scif0_clk_pins[] = {
3289 /* SCK */
3290 RCAR_GP_PIN(5, 0),
3291};
3292static const unsigned int scif0_clk_mux[] = {
3293 SCK0_MARK,
3294};
3295static const unsigned int scif0_ctrl_pins[] = {
3296 /* RTS, CTS */
3297 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3298};
3299static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3300 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3301};
3302/* - SCIF1 ------------------------------------------------------------------ */
3303static const unsigned int scif1_data_a_pins[] = {
3304 /* RX, TX */
3305 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3306};
3307static const unsigned int scif1_data_a_mux[] = {
3308 RX1_A_MARK, TX1_A_MARK,
3309};
3310static const unsigned int scif1_clk_pins[] = {
3311 /* SCK */
3312 RCAR_GP_PIN(6, 21),
3313};
3314static const unsigned int scif1_clk_mux[] = {
3315 SCK1_MARK,
3316};
3317static const unsigned int scif1_ctrl_pins[] = {
3318 /* RTS, CTS */
3319 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3320};
3321static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3322 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3323};
3324
3325static const unsigned int scif1_data_b_pins[] = {
3326 /* RX, TX */
3327 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3328};
3329static const unsigned int scif1_data_b_mux[] = {
3330 RX1_B_MARK, TX1_B_MARK,
3331};
3332/* - SCIF2 ------------------------------------------------------------------ */
3333static const unsigned int scif2_data_a_pins[] = {
3334 /* RX, TX */
3335 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3336};
3337static const unsigned int scif2_data_a_mux[] = {
3338 RX2_A_MARK, TX2_A_MARK,
3339};
3340static const unsigned int scif2_clk_pins[] = {
3341 /* SCK */
3342 RCAR_GP_PIN(5, 9),
3343};
3344static const unsigned int scif2_clk_mux[] = {
3345 SCK2_MARK,
3346};
3347static const unsigned int scif2_data_b_pins[] = {
3348 /* RX, TX */
3349 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3350};
3351static const unsigned int scif2_data_b_mux[] = {
3352 RX2_B_MARK, TX2_B_MARK,
3353};
3354/* - SCIF3 ------------------------------------------------------------------ */
3355static const unsigned int scif3_data_a_pins[] = {
3356 /* RX, TX */
3357 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3358};
3359static const unsigned int scif3_data_a_mux[] = {
3360 RX3_A_MARK, TX3_A_MARK,
3361};
3362static const unsigned int scif3_clk_pins[] = {
3363 /* SCK */
3364 RCAR_GP_PIN(1, 22),
3365};
3366static const unsigned int scif3_clk_mux[] = {
3367 SCK3_MARK,
3368};
3369static const unsigned int scif3_ctrl_pins[] = {
3370 /* RTS, CTS */
3371 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3372};
3373static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3374 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3375};
3376static const unsigned int scif3_data_b_pins[] = {
3377 /* RX, TX */
3378 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3379};
3380static const unsigned int scif3_data_b_mux[] = {
3381 RX3_B_MARK, TX3_B_MARK,
3382};
3383/* - SCIF4 ------------------------------------------------------------------ */
3384static const unsigned int scif4_data_a_pins[] = {
3385 /* RX, TX */
3386 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3387};
3388static const unsigned int scif4_data_a_mux[] = {
3389 RX4_A_MARK, TX4_A_MARK,
3390};
3391static const unsigned int scif4_clk_a_pins[] = {
3392 /* SCK */
3393 RCAR_GP_PIN(2, 10),
3394};
3395static const unsigned int scif4_clk_a_mux[] = {
3396 SCK4_A_MARK,
3397};
3398static const unsigned int scif4_ctrl_a_pins[] = {
3399 /* RTS, CTS */
3400 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3401};
3402static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3403 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3404};
3405static const unsigned int scif4_data_b_pins[] = {
3406 /* RX, TX */
3407 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3408};
3409static const unsigned int scif4_data_b_mux[] = {
3410 RX4_B_MARK, TX4_B_MARK,
3411};
3412static const unsigned int scif4_clk_b_pins[] = {
3413 /* SCK */
3414 RCAR_GP_PIN(1, 5),
3415};
3416static const unsigned int scif4_clk_b_mux[] = {
3417 SCK4_B_MARK,
3418};
3419static const unsigned int scif4_ctrl_b_pins[] = {
3420 /* RTS, CTS */
3421 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3422};
3423static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3424 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3425};
3426static const unsigned int scif4_data_c_pins[] = {
3427 /* RX, TX */
3428 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3429};
3430static const unsigned int scif4_data_c_mux[] = {
3431 RX4_C_MARK, TX4_C_MARK,
3432};
3433static const unsigned int scif4_clk_c_pins[] = {
3434 /* SCK */
3435 RCAR_GP_PIN(0, 8),
3436};
3437static const unsigned int scif4_clk_c_mux[] = {
3438 SCK4_C_MARK,
3439};
3440static const unsigned int scif4_ctrl_c_pins[] = {
3441 /* RTS, CTS */
3442 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3443};
3444static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3445 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3446};
3447/* - SCIF5 ------------------------------------------------------------------ */
3448static const unsigned int scif5_data_a_pins[] = {
3449 /* RX, TX */
3450 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3451};
3452static const unsigned int scif5_data_a_mux[] = {
3453 RX5_A_MARK, TX5_A_MARK,
3454};
3455static const unsigned int scif5_clk_a_pins[] = {
3456 /* SCK */
3457 RCAR_GP_PIN(6, 21),
3458};
3459static const unsigned int scif5_clk_a_mux[] = {
3460 SCK5_A_MARK,
3461};
3462static const unsigned int scif5_data_b_pins[] = {
3463 /* RX, TX */
3464 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3465};
3466static const unsigned int scif5_data_b_mux[] = {
3467 RX5_B_MARK, TX5_B_MARK,
3468};
3469static const unsigned int scif5_clk_b_pins[] = {
3470 /* SCK */
3471 RCAR_GP_PIN(5, 0),
3472};
3473static const unsigned int scif5_clk_b_mux[] = {
3474 SCK5_B_MARK,
3475};
3476
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3477/* - SCIF Clock ------------------------------------------------------------- */
3478static const unsigned int scif_clk_a_pins[] = {
3479 /* SCIF_CLK */
3480 RCAR_GP_PIN(6, 23),
3481};
3482static const unsigned int scif_clk_a_mux[] = {
3483 SCIF_CLK_A_MARK,
3484};
3485static const unsigned int scif_clk_b_pins[] = {
3486 /* SCIF_CLK */
3487 RCAR_GP_PIN(5, 9),
3488};
3489static const unsigned int scif_clk_b_mux[] = {
3490 SCIF_CLK_B_MARK,
3491};
3492
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3493/* - SDHI0 ------------------------------------------------------------------ */
3494static const unsigned int sdhi0_data1_pins[] = {
3495 /* D0 */
3496 RCAR_GP_PIN(3, 2),
3497};
3498static const unsigned int sdhi0_data1_mux[] = {
3499 SD0_DAT0_MARK,
3500};
3501static const unsigned int sdhi0_data4_pins[] = {
3502 /* D[0:3] */
3503 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3504 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3505};
3506static const unsigned int sdhi0_data4_mux[] = {
3507 SD0_DAT0_MARK, SD0_DAT1_MARK,
3508 SD0_DAT2_MARK, SD0_DAT3_MARK,
3509};
3510static const unsigned int sdhi0_ctrl_pins[] = {
3511 /* CLK, CMD */
3512 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3513};
3514static const unsigned int sdhi0_ctrl_mux[] = {
3515 SD0_CLK_MARK, SD0_CMD_MARK,
3516};
3517static const unsigned int sdhi0_cd_pins[] = {
3518 /* CD */
3519 RCAR_GP_PIN(3, 12),
3520};
3521static const unsigned int sdhi0_cd_mux[] = {
3522 SD0_CD_MARK,
3523};
3524static const unsigned int sdhi0_wp_pins[] = {
3525 /* WP */
3526 RCAR_GP_PIN(3, 13),
3527};
3528static const unsigned int sdhi0_wp_mux[] = {
3529 SD0_WP_MARK,
3530};
3531/* - SDHI1 ------------------------------------------------------------------ */
3532static const unsigned int sdhi1_data1_pins[] = {
3533 /* D0 */
3534 RCAR_GP_PIN(3, 8),
3535};
3536static const unsigned int sdhi1_data1_mux[] = {
3537 SD1_DAT0_MARK,
3538};
3539static const unsigned int sdhi1_data4_pins[] = {
3540 /* D[0:3] */
3541 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3542 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3543};
3544static const unsigned int sdhi1_data4_mux[] = {
3545 SD1_DAT0_MARK, SD1_DAT1_MARK,
3546 SD1_DAT2_MARK, SD1_DAT3_MARK,
3547};
3548static const unsigned int sdhi1_ctrl_pins[] = {
3549 /* CLK, CMD */
3550 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3551};
3552static const unsigned int sdhi1_ctrl_mux[] = {
3553 SD1_CLK_MARK, SD1_CMD_MARK,
3554};
3555static const unsigned int sdhi1_cd_pins[] = {
3556 /* CD */
3557 RCAR_GP_PIN(3, 14),
3558};
3559static const unsigned int sdhi1_cd_mux[] = {
3560 SD1_CD_MARK,
3561};
3562static const unsigned int sdhi1_wp_pins[] = {
3563 /* WP */
3564 RCAR_GP_PIN(3, 15),
3565};
3566static const unsigned int sdhi1_wp_mux[] = {
3567 SD1_WP_MARK,
3568};
3569/* - SDHI2 ------------------------------------------------------------------ */
3570static const unsigned int sdhi2_data1_pins[] = {
3571 /* D0 */
3572 RCAR_GP_PIN(4, 2),
3573};
3574static const unsigned int sdhi2_data1_mux[] = {
3575 SD2_DAT0_MARK,
3576};
3577static const unsigned int sdhi2_data4_pins[] = {
3578 /* D[0:3] */
3579 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3580 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3581};
3582static const unsigned int sdhi2_data4_mux[] = {
3583 SD2_DAT0_MARK, SD2_DAT1_MARK,
3584 SD2_DAT2_MARK, SD2_DAT3_MARK,
3585};
3586static const unsigned int sdhi2_data8_pins[] = {
3587 /* D[0:7] */
3588 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3589 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3590 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3591 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3592};
3593static const unsigned int sdhi2_data8_mux[] = {
3594 SD2_DAT0_MARK, SD2_DAT1_MARK,
3595 SD2_DAT2_MARK, SD2_DAT3_MARK,
3596 SD2_DAT4_MARK, SD2_DAT5_MARK,
3597 SD2_DAT6_MARK, SD2_DAT7_MARK,
3598};
3599static const unsigned int sdhi2_ctrl_pins[] = {
3600 /* CLK, CMD */
3601 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3602};
3603static const unsigned int sdhi2_ctrl_mux[] = {
3604 SD2_CLK_MARK, SD2_CMD_MARK,
3605};
3606static const unsigned int sdhi2_cd_a_pins[] = {
3607 /* CD */
3608 RCAR_GP_PIN(4, 13),
3609};
3610static const unsigned int sdhi2_cd_a_mux[] = {
3611 SD2_CD_A_MARK,
3612};
3613static const unsigned int sdhi2_cd_b_pins[] = {
3614 /* CD */
3615 RCAR_GP_PIN(5, 10),
3616};
3617static const unsigned int sdhi2_cd_b_mux[] = {
3618 SD2_CD_B_MARK,
3619};
3620static const unsigned int sdhi2_wp_a_pins[] = {
3621 /* WP */
3622 RCAR_GP_PIN(4, 14),
3623};
3624static const unsigned int sdhi2_wp_a_mux[] = {
3625 SD2_WP_A_MARK,
3626};
3627static const unsigned int sdhi2_wp_b_pins[] = {
3628 /* WP */
3629 RCAR_GP_PIN(5, 11),
3630};
3631static const unsigned int sdhi2_wp_b_mux[] = {
3632 SD2_WP_B_MARK,
3633};
3634static const unsigned int sdhi2_ds_pins[] = {
3635 /* DS */
3636 RCAR_GP_PIN(4, 6),
3637};
3638static const unsigned int sdhi2_ds_mux[] = {
3639 SD2_DS_MARK,
3640};
3641/* - SDHI3 ------------------------------------------------------------------ */
3642static const unsigned int sdhi3_data1_pins[] = {
3643 /* D0 */
3644 RCAR_GP_PIN(4, 9),
3645};
3646static const unsigned int sdhi3_data1_mux[] = {
3647 SD3_DAT0_MARK,
3648};
3649static const unsigned int sdhi3_data4_pins[] = {
3650 /* D[0:3] */
3651 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3652 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3653};
3654static const unsigned int sdhi3_data4_mux[] = {
3655 SD3_DAT0_MARK, SD3_DAT1_MARK,
3656 SD3_DAT2_MARK, SD3_DAT3_MARK,
3657};
3658static const unsigned int sdhi3_data8_pins[] = {
3659 /* D[0:7] */
3660 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3661 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3662 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3663 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3664};
3665static const unsigned int sdhi3_data8_mux[] = {
3666 SD3_DAT0_MARK, SD3_DAT1_MARK,
3667 SD3_DAT2_MARK, SD3_DAT3_MARK,
3668 SD3_DAT4_MARK, SD3_DAT5_MARK,
3669 SD3_DAT6_MARK, SD3_DAT7_MARK,
3670};
3671static const unsigned int sdhi3_ctrl_pins[] = {
3672 /* CLK, CMD */
3673 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3674};
3675static const unsigned int sdhi3_ctrl_mux[] = {
3676 SD3_CLK_MARK, SD3_CMD_MARK,
3677};
3678static const unsigned int sdhi3_cd_pins[] = {
3679 /* CD */
3680 RCAR_GP_PIN(4, 15),
3681};
3682static const unsigned int sdhi3_cd_mux[] = {
3683 SD3_CD_MARK,
3684};
3685static const unsigned int sdhi3_wp_pins[] = {
3686 /* WP */
3687 RCAR_GP_PIN(4, 16),
3688};
3689static const unsigned int sdhi3_wp_mux[] = {
3690 SD3_WP_MARK,
3691};
3692static const unsigned int sdhi3_ds_pins[] = {
3693 /* DS */
3694 RCAR_GP_PIN(4, 17),
3695};
3696static const unsigned int sdhi3_ds_mux[] = {
3697 SD3_DS_MARK,
3698};
3699
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3700/* - SSI -------------------------------------------------------------------- */
3701static const unsigned int ssi0_data_pins[] = {
3702 /* SDATA */
3703 RCAR_GP_PIN(6, 2),
3704};
3705static const unsigned int ssi0_data_mux[] = {
3706 SSI_SDATA0_MARK,
3707};
3708static const unsigned int ssi01239_ctrl_pins[] = {
3709 /* SCK, WS */
3710 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3711};
3712static const unsigned int ssi01239_ctrl_mux[] = {
3713 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3714};
3715static const unsigned int ssi1_data_a_pins[] = {
3716 /* SDATA */
3717 RCAR_GP_PIN(6, 3),
3718};
3719static const unsigned int ssi1_data_a_mux[] = {
3720 SSI_SDATA1_A_MARK,
3721};
3722static const unsigned int ssi1_data_b_pins[] = {
3723 /* SDATA */
3724 RCAR_GP_PIN(5, 12),
3725};
3726static const unsigned int ssi1_data_b_mux[] = {
3727 SSI_SDATA1_B_MARK,
3728};
3729static const unsigned int ssi1_ctrl_a_pins[] = {
3730 /* SCK, WS */
3731 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3732};
3733static const unsigned int ssi1_ctrl_a_mux[] = {
3734 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3735};
3736static const unsigned int ssi1_ctrl_b_pins[] = {
3737 /* SCK, WS */
3738 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3739};
3740static const unsigned int ssi1_ctrl_b_mux[] = {
3741 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3742};
3743static const unsigned int ssi2_data_a_pins[] = {
3744 /* SDATA */
3745 RCAR_GP_PIN(6, 4),
3746};
3747static const unsigned int ssi2_data_a_mux[] = {
3748 SSI_SDATA2_A_MARK,
3749};
3750static const unsigned int ssi2_data_b_pins[] = {
3751 /* SDATA */
3752 RCAR_GP_PIN(5, 13),
3753};
3754static const unsigned int ssi2_data_b_mux[] = {
3755 SSI_SDATA2_B_MARK,
3756};
3757static const unsigned int ssi2_ctrl_a_pins[] = {
3758 /* SCK, WS */
3759 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3760};
3761static const unsigned int ssi2_ctrl_a_mux[] = {
3762 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3763};
3764static const unsigned int ssi2_ctrl_b_pins[] = {
3765 /* SCK, WS */
3766 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3767};
3768static const unsigned int ssi2_ctrl_b_mux[] = {
3769 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3770};
3771static const unsigned int ssi3_data_pins[] = {
3772 /* SDATA */
3773 RCAR_GP_PIN(6, 7),
3774};
3775static const unsigned int ssi3_data_mux[] = {
3776 SSI_SDATA3_MARK,
3777};
3778static const unsigned int ssi349_ctrl_pins[] = {
3779 /* SCK, WS */
3780 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3781};
3782static const unsigned int ssi349_ctrl_mux[] = {
3783 SSI_SCK349_MARK, SSI_WS349_MARK,
3784};
3785static const unsigned int ssi4_data_pins[] = {
3786 /* SDATA */
3787 RCAR_GP_PIN(6, 10),
3788};
3789static const unsigned int ssi4_data_mux[] = {
3790 SSI_SDATA4_MARK,
3791};
3792static const unsigned int ssi4_ctrl_pins[] = {
3793 /* SCK, WS */
3794 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3795};
3796static const unsigned int ssi4_ctrl_mux[] = {
3797 SSI_SCK4_MARK, SSI_WS4_MARK,
3798};
3799static const unsigned int ssi5_data_pins[] = {
3800 /* SDATA */
3801 RCAR_GP_PIN(6, 13),
3802};
3803static const unsigned int ssi5_data_mux[] = {
3804 SSI_SDATA5_MARK,
3805};
3806static const unsigned int ssi5_ctrl_pins[] = {
3807 /* SCK, WS */
3808 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3809};
3810static const unsigned int ssi5_ctrl_mux[] = {
3811 SSI_SCK5_MARK, SSI_WS5_MARK,
3812};
3813static const unsigned int ssi6_data_pins[] = {
3814 /* SDATA */
3815 RCAR_GP_PIN(6, 16),
3816};
3817static const unsigned int ssi6_data_mux[] = {
3818 SSI_SDATA6_MARK,
3819};
3820static const unsigned int ssi6_ctrl_pins[] = {
3821 /* SCK, WS */
3822 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3823};
3824static const unsigned int ssi6_ctrl_mux[] = {
3825 SSI_SCK6_MARK, SSI_WS6_MARK,
3826};
3827static const unsigned int ssi7_data_pins[] = {
3828 /* SDATA */
3829 RCAR_GP_PIN(6, 19),
3830};
3831static const unsigned int ssi7_data_mux[] = {
3832 SSI_SDATA7_MARK,
3833};
3834static const unsigned int ssi78_ctrl_pins[] = {
3835 /* SCK, WS */
3836 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3837};
3838static const unsigned int ssi78_ctrl_mux[] = {
3839 SSI_SCK78_MARK, SSI_WS78_MARK,
3840};
3841static const unsigned int ssi8_data_pins[] = {
3842 /* SDATA */
3843 RCAR_GP_PIN(6, 20),
3844};
3845static const unsigned int ssi8_data_mux[] = {
3846 SSI_SDATA8_MARK,
3847};
3848static const unsigned int ssi9_data_a_pins[] = {
3849 /* SDATA */
3850 RCAR_GP_PIN(6, 21),
3851};
3852static const unsigned int ssi9_data_a_mux[] = {
3853 SSI_SDATA9_A_MARK,
3854};
3855static const unsigned int ssi9_data_b_pins[] = {
3856 /* SDATA */
3857 RCAR_GP_PIN(5, 14),
3858};
3859static const unsigned int ssi9_data_b_mux[] = {
3860 SSI_SDATA9_B_MARK,
3861};
3862static const unsigned int ssi9_ctrl_a_pins[] = {
3863 /* SCK, WS */
3864 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3865};
3866static const unsigned int ssi9_ctrl_a_mux[] = {
3867 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3868};
3869static const unsigned int ssi9_ctrl_b_pins[] = {
3870 /* SCK, WS */
3871 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3872};
3873static const unsigned int ssi9_ctrl_b_mux[] = {
3874 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3875};
3876
3877/* - TMU -------------------------------------------------------------------- */
3878static const unsigned int tmu_tclk1_a_pins[] = {
3879 /* TCLK */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3880 RCAR_GP_PIN(6, 23),
3881};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3882static const unsigned int tmu_tclk1_a_mux[] = {
3883 TCLK1_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3884};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3885static const unsigned int tmu_tclk1_b_pins[] = {
3886 /* TCLK */
3887 RCAR_GP_PIN(5, 19),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3888};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3889static const unsigned int tmu_tclk1_b_mux[] = {
3890 TCLK1_B_MARK,
3891};
3892static const unsigned int tmu_tclk2_a_pins[] = {
3893 /* TCLK */
3894 RCAR_GP_PIN(6, 19),
3895};
3896static const unsigned int tmu_tclk2_a_mux[] = {
3897 TCLK2_A_MARK,
3898};
3899static const unsigned int tmu_tclk2_b_pins[] = {
3900 /* TCLK */
3901 RCAR_GP_PIN(6, 28),
3902};
3903static const unsigned int tmu_tclk2_b_mux[] = {
3904 TCLK2_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3905};
3906
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]3907/* - TPU ------------------------------------------------------------------- */
3908static const unsigned int tpu_to0_pins[] = {
3909 /* TPU0TO0 */
3910 RCAR_GP_PIN(6, 28),
3911};
3912static const unsigned int tpu_to0_mux[] = {
3913 TPU0TO0_MARK,
3914};
3915static const unsigned int tpu_to1_pins[] = {
3916 /* TPU0TO1 */
3917 RCAR_GP_PIN(6, 29),
3918};
3919static const unsigned int tpu_to1_mux[] = {
3920 TPU0TO1_MARK,
3921};
3922static const unsigned int tpu_to2_pins[] = {
3923 /* TPU0TO2 */
3924 RCAR_GP_PIN(6, 30),
3925};
3926static const unsigned int tpu_to2_mux[] = {
3927 TPU0TO2_MARK,
3928};
3929static const unsigned int tpu_to3_pins[] = {
3930 /* TPU0TO3 */
3931 RCAR_GP_PIN(6, 31),
3932};
3933static const unsigned int tpu_to3_mux[] = {
3934 TPU0TO3_MARK,
3935};
3936
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3937/* - USB0 ------------------------------------------------------------------- */
3938static const unsigned int usb0_pins[] = {
3939 /* PWEN, OVC */
3940 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3941};
3942static const unsigned int usb0_mux[] = {
3943 USB0_PWEN_MARK, USB0_OVC_MARK,
3944};
3945/* - USB1 ------------------------------------------------------------------- */
3946static const unsigned int usb1_pins[] = {
3947 /* PWEN, OVC */
3948 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3949};
3950static const unsigned int usb1_mux[] = {
3951 USB1_PWEN_MARK, USB1_OVC_MARK,
3952};
3953/* - USB2 ------------------------------------------------------------------- */
3954static const unsigned int usb2_pins[] = {
3955 /* PWEN, OVC */
3956 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3957};
3958static const unsigned int usb2_mux[] = {
3959 USB2_PWEN_MARK, USB2_OVC_MARK,
3960};
3961/* - USB2_CH3 --------------------------------------------------------------- */
3962static const unsigned int usb2_ch3_pins[] = {
3963 /* PWEN, OVC */
3964 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3965};
3966static const unsigned int usb2_ch3_mux[] = {
3967 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3968};
3969
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3970/* - USB30 ------------------------------------------------------------------ */
3971static const unsigned int usb30_pins[] = {
3972 /* PWEN, OVC */
3973 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3974};
3975static const unsigned int usb30_mux[] = {
3976 USB30_PWEN_MARK, USB30_OVC_MARK,
3977};
3978
3979/* - VIN4 ------------------------------------------------------------------- */
3980static const unsigned int vin4_data18_a_pins[] = {
3981 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3982 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3983 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3984 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3985 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3986 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3987 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3988 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3989 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3990};
3991static const unsigned int vin4_data18_a_mux[] = {
3992 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3993 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3994 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3995 VI4_DATA10_MARK, VI4_DATA11_MARK,
3996 VI4_DATA12_MARK, VI4_DATA13_MARK,
3997 VI4_DATA14_MARK, VI4_DATA15_MARK,
3998 VI4_DATA18_MARK, VI4_DATA19_MARK,
3999 VI4_DATA20_MARK, VI4_DATA21_MARK,
4000 VI4_DATA22_MARK, VI4_DATA23_MARK,
4001};
4002static const unsigned int vin4_data18_b_pins[] = {
4003 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4004 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4005 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4006 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4007 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4008 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4009 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4010 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4011 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4012};
4013static const unsigned int vin4_data18_b_mux[] = {
4014 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4015 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4016 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4017 VI4_DATA10_MARK, VI4_DATA11_MARK,
4018 VI4_DATA12_MARK, VI4_DATA13_MARK,
4019 VI4_DATA14_MARK, VI4_DATA15_MARK,
4020 VI4_DATA18_MARK, VI4_DATA19_MARK,
4021 VI4_DATA20_MARK, VI4_DATA21_MARK,
4022 VI4_DATA22_MARK, VI4_DATA23_MARK,
4023};
4024static const union vin_data vin4_data_a_pins = {
4025 .data24 = {
4026 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4027 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4028 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4029 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4030 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4031 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4032 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4033 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4034 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4035 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4036 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4037 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4038 },
4039};
4040static const union vin_data vin4_data_a_mux = {
4041 .data24 = {
4042 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4043 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4044 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4045 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4046 VI4_DATA8_MARK, VI4_DATA9_MARK,
4047 VI4_DATA10_MARK, VI4_DATA11_MARK,
4048 VI4_DATA12_MARK, VI4_DATA13_MARK,
4049 VI4_DATA14_MARK, VI4_DATA15_MARK,
4050 VI4_DATA16_MARK, VI4_DATA17_MARK,
4051 VI4_DATA18_MARK, VI4_DATA19_MARK,
4052 VI4_DATA20_MARK, VI4_DATA21_MARK,
4053 VI4_DATA22_MARK, VI4_DATA23_MARK,
4054 },
4055};
4056static const union vin_data vin4_data_b_pins = {
4057 .data24 = {
4058 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4059 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4060 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4061 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4062 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4063 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4064 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4065 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4066 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4067 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4068 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4069 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4070 },
4071};
4072static const union vin_data vin4_data_b_mux = {
4073 .data24 = {
4074 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4075 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4076 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4077 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4078 VI4_DATA8_MARK, VI4_DATA9_MARK,
4079 VI4_DATA10_MARK, VI4_DATA11_MARK,
4080 VI4_DATA12_MARK, VI4_DATA13_MARK,
4081 VI4_DATA14_MARK, VI4_DATA15_MARK,
4082 VI4_DATA16_MARK, VI4_DATA17_MARK,
4083 VI4_DATA18_MARK, VI4_DATA19_MARK,
4084 VI4_DATA20_MARK, VI4_DATA21_MARK,
4085 VI4_DATA22_MARK, VI4_DATA23_MARK,
4086 },
4087};
4088static const unsigned int vin4_sync_pins[] = {
4089 /* HSYNC#, VSYNC# */
4090 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4091};
4092static const unsigned int vin4_sync_mux[] = {
4093 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4094};
4095static const unsigned int vin4_field_pins[] = {
4096 /* FIELD */
4097 RCAR_GP_PIN(1, 16),
4098};
4099static const unsigned int vin4_field_mux[] = {
4100 VI4_FIELD_MARK,
4101};
4102static const unsigned int vin4_clkenb_pins[] = {
4103 /* CLKENB */
4104 RCAR_GP_PIN(1, 19),
4105};
4106static const unsigned int vin4_clkenb_mux[] = {
4107 VI4_CLKENB_MARK,
4108};
4109static const unsigned int vin4_clk_pins[] = {
4110 /* CLK */
4111 RCAR_GP_PIN(1, 27),
4112};
4113static const unsigned int vin4_clk_mux[] = {
4114 VI4_CLK_MARK,
4115};
4116
4117/* - VIN5 ------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4118static const union vin_data16 vin5_data_pins = {
4119 .data16 = {
4120 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4121 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4122 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4123 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4124 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4125 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4126 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4127 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4128 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4129};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4130static const union vin_data16 vin5_data_mux = {
4131 .data16 = {
4132 VI5_DATA0_MARK, VI5_DATA1_MARK,
4133 VI5_DATA2_MARK, VI5_DATA3_MARK,
4134 VI5_DATA4_MARK, VI5_DATA5_MARK,
4135 VI5_DATA6_MARK, VI5_DATA7_MARK,
4136 VI5_DATA8_MARK, VI5_DATA9_MARK,
4137 VI5_DATA10_MARK, VI5_DATA11_MARK,
4138 VI5_DATA12_MARK, VI5_DATA13_MARK,
4139 VI5_DATA14_MARK, VI5_DATA15_MARK,
4140 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4141};
4142static const unsigned int vin5_sync_pins[] = {
4143 /* HSYNC#, VSYNC# */
4144 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4145};
4146static const unsigned int vin5_sync_mux[] = {
4147 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4148};
4149static const unsigned int vin5_field_pins[] = {
4150 RCAR_GP_PIN(1, 11),
4151};
4152static const unsigned int vin5_field_mux[] = {
4153 /* FIELD */
4154 VI5_FIELD_MARK,
4155};
4156static const unsigned int vin5_clkenb_pins[] = {
4157 RCAR_GP_PIN(1, 20),
4158};
4159static const unsigned int vin5_clkenb_mux[] = {
4160 /* CLKENB */
4161 VI5_CLKENB_MARK,
4162};
4163static const unsigned int vin5_clk_pins[] = {
4164 RCAR_GP_PIN(1, 21),
4165};
4166static const unsigned int vin5_clk_mux[] = {
4167 /* CLK */
4168 VI5_CLK_MARK,
4169};
4170
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4171static const struct {
4172 struct sh_pfc_pin_group common[320];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4173#ifdef CONFIG_PINCTRL_PFC_R8A7795
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4174 struct sh_pfc_pin_group automotive[30];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4175#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4176} pinmux_groups = {
4177 .common = {
4178 SH_PFC_PIN_GROUP(audio_clk_a_a),
4179 SH_PFC_PIN_GROUP(audio_clk_a_b),
4180 SH_PFC_PIN_GROUP(audio_clk_a_c),
4181 SH_PFC_PIN_GROUP(audio_clk_b_a),
4182 SH_PFC_PIN_GROUP(audio_clk_b_b),
4183 SH_PFC_PIN_GROUP(audio_clk_c_a),
4184 SH_PFC_PIN_GROUP(audio_clk_c_b),
4185 SH_PFC_PIN_GROUP(audio_clkout_a),
4186 SH_PFC_PIN_GROUP(audio_clkout_b),
4187 SH_PFC_PIN_GROUP(audio_clkout_c),
4188 SH_PFC_PIN_GROUP(audio_clkout_d),
4189 SH_PFC_PIN_GROUP(audio_clkout1_a),
4190 SH_PFC_PIN_GROUP(audio_clkout1_b),
4191 SH_PFC_PIN_GROUP(audio_clkout2_a),
4192 SH_PFC_PIN_GROUP(audio_clkout2_b),
4193 SH_PFC_PIN_GROUP(audio_clkout3_a),
4194 SH_PFC_PIN_GROUP(audio_clkout3_b),
4195 SH_PFC_PIN_GROUP(avb_link),
4196 SH_PFC_PIN_GROUP(avb_magic),
4197 SH_PFC_PIN_GROUP(avb_phy_int),
4198 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4199 SH_PFC_PIN_GROUP(avb_mdio),
4200 SH_PFC_PIN_GROUP(avb_mii),
4201 SH_PFC_PIN_GROUP(avb_avtp_pps),
4202 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4203 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4204 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4205 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4206 SH_PFC_PIN_GROUP(can0_data_a),
4207 SH_PFC_PIN_GROUP(can0_data_b),
4208 SH_PFC_PIN_GROUP(can1_data),
4209 SH_PFC_PIN_GROUP(can_clk),
4210 SH_PFC_PIN_GROUP(canfd0_data_a),
4211 SH_PFC_PIN_GROUP(canfd0_data_b),
4212 SH_PFC_PIN_GROUP(canfd1_data),
4213 SH_PFC_PIN_GROUP(du_rgb666),
4214 SH_PFC_PIN_GROUP(du_rgb888),
4215 SH_PFC_PIN_GROUP(du_clk_out_0),
4216 SH_PFC_PIN_GROUP(du_clk_out_1),
4217 SH_PFC_PIN_GROUP(du_sync),
4218 SH_PFC_PIN_GROUP(du_oddf),
4219 SH_PFC_PIN_GROUP(du_cde),
4220 SH_PFC_PIN_GROUP(du_disp),
4221 SH_PFC_PIN_GROUP(hscif0_data),
4222 SH_PFC_PIN_GROUP(hscif0_clk),
4223 SH_PFC_PIN_GROUP(hscif0_ctrl),
4224 SH_PFC_PIN_GROUP(hscif1_data_a),
4225 SH_PFC_PIN_GROUP(hscif1_clk_a),
4226 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4227 SH_PFC_PIN_GROUP(hscif1_data_b),
4228 SH_PFC_PIN_GROUP(hscif1_clk_b),
4229 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4230 SH_PFC_PIN_GROUP(hscif2_data_a),
4231 SH_PFC_PIN_GROUP(hscif2_clk_a),
4232 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4233 SH_PFC_PIN_GROUP(hscif2_data_b),
4234 SH_PFC_PIN_GROUP(hscif2_clk_b),
4235 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4236 SH_PFC_PIN_GROUP(hscif2_data_c),
4237 SH_PFC_PIN_GROUP(hscif2_clk_c),
4238 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4239 SH_PFC_PIN_GROUP(hscif3_data_a),
4240 SH_PFC_PIN_GROUP(hscif3_clk),
4241 SH_PFC_PIN_GROUP(hscif3_ctrl),
4242 SH_PFC_PIN_GROUP(hscif3_data_b),
4243 SH_PFC_PIN_GROUP(hscif3_data_c),
4244 SH_PFC_PIN_GROUP(hscif3_data_d),
4245 SH_PFC_PIN_GROUP(hscif4_data_a),
4246 SH_PFC_PIN_GROUP(hscif4_clk),
4247 SH_PFC_PIN_GROUP(hscif4_ctrl),
4248 SH_PFC_PIN_GROUP(hscif4_data_b),
4249 SH_PFC_PIN_GROUP(i2c0),
4250 SH_PFC_PIN_GROUP(i2c1_a),
4251 SH_PFC_PIN_GROUP(i2c1_b),
4252 SH_PFC_PIN_GROUP(i2c2_a),
4253 SH_PFC_PIN_GROUP(i2c2_b),
4254 SH_PFC_PIN_GROUP(i2c3),
4255 SH_PFC_PIN_GROUP(i2c5),
4256 SH_PFC_PIN_GROUP(i2c6_a),
4257 SH_PFC_PIN_GROUP(i2c6_b),
4258 SH_PFC_PIN_GROUP(i2c6_c),
4259 SH_PFC_PIN_GROUP(intc_ex_irq0),
4260 SH_PFC_PIN_GROUP(intc_ex_irq1),
4261 SH_PFC_PIN_GROUP(intc_ex_irq2),
4262 SH_PFC_PIN_GROUP(intc_ex_irq3),
4263 SH_PFC_PIN_GROUP(intc_ex_irq4),
4264 SH_PFC_PIN_GROUP(intc_ex_irq5),
4265 SH_PFC_PIN_GROUP(msiof0_clk),
4266 SH_PFC_PIN_GROUP(msiof0_sync),
4267 SH_PFC_PIN_GROUP(msiof0_ss1),
4268 SH_PFC_PIN_GROUP(msiof0_ss2),
4269 SH_PFC_PIN_GROUP(msiof0_txd),
4270 SH_PFC_PIN_GROUP(msiof0_rxd),
4271 SH_PFC_PIN_GROUP(msiof1_clk_a),
4272 SH_PFC_PIN_GROUP(msiof1_sync_a),
4273 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4274 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4275 SH_PFC_PIN_GROUP(msiof1_txd_a),
4276 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4277 SH_PFC_PIN_GROUP(msiof1_clk_b),
4278 SH_PFC_PIN_GROUP(msiof1_sync_b),
4279 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4280 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4281 SH_PFC_PIN_GROUP(msiof1_txd_b),
4282 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4283 SH_PFC_PIN_GROUP(msiof1_clk_c),
4284 SH_PFC_PIN_GROUP(msiof1_sync_c),
4285 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4286 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4287 SH_PFC_PIN_GROUP(msiof1_txd_c),
4288 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4289 SH_PFC_PIN_GROUP(msiof1_clk_d),
4290 SH_PFC_PIN_GROUP(msiof1_sync_d),
4291 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4292 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4293 SH_PFC_PIN_GROUP(msiof1_txd_d),
4294 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4295 SH_PFC_PIN_GROUP(msiof1_clk_e),
4296 SH_PFC_PIN_GROUP(msiof1_sync_e),
4297 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4298 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4299 SH_PFC_PIN_GROUP(msiof1_txd_e),
4300 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4301 SH_PFC_PIN_GROUP(msiof1_clk_f),
4302 SH_PFC_PIN_GROUP(msiof1_sync_f),
4303 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4304 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4305 SH_PFC_PIN_GROUP(msiof1_txd_f),
4306 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4307 SH_PFC_PIN_GROUP(msiof1_clk_g),
4308 SH_PFC_PIN_GROUP(msiof1_sync_g),
4309 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4310 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4311 SH_PFC_PIN_GROUP(msiof1_txd_g),
4312 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4313 SH_PFC_PIN_GROUP(msiof2_clk_a),
4314 SH_PFC_PIN_GROUP(msiof2_sync_a),
4315 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4316 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4317 SH_PFC_PIN_GROUP(msiof2_txd_a),
4318 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4319 SH_PFC_PIN_GROUP(msiof2_clk_b),
4320 SH_PFC_PIN_GROUP(msiof2_sync_b),
4321 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4322 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4323 SH_PFC_PIN_GROUP(msiof2_txd_b),
4324 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4325 SH_PFC_PIN_GROUP(msiof2_clk_c),
4326 SH_PFC_PIN_GROUP(msiof2_sync_c),
4327 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4328 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4329 SH_PFC_PIN_GROUP(msiof2_txd_c),
4330 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4331 SH_PFC_PIN_GROUP(msiof2_clk_d),
4332 SH_PFC_PIN_GROUP(msiof2_sync_d),
4333 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4334 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4335 SH_PFC_PIN_GROUP(msiof2_txd_d),
4336 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4337 SH_PFC_PIN_GROUP(msiof3_clk_a),
4338 SH_PFC_PIN_GROUP(msiof3_sync_a),
4339 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4340 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4341 SH_PFC_PIN_GROUP(msiof3_txd_a),
4342 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4343 SH_PFC_PIN_GROUP(msiof3_clk_b),
4344 SH_PFC_PIN_GROUP(msiof3_sync_b),
4345 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4346 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4347 SH_PFC_PIN_GROUP(msiof3_txd_b),
4348 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4349 SH_PFC_PIN_GROUP(msiof3_clk_c),
4350 SH_PFC_PIN_GROUP(msiof3_sync_c),
4351 SH_PFC_PIN_GROUP(msiof3_txd_c),
4352 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4353 SH_PFC_PIN_GROUP(msiof3_clk_d),
4354 SH_PFC_PIN_GROUP(msiof3_sync_d),
4355 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4356 SH_PFC_PIN_GROUP(msiof3_txd_d),
4357 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4358 SH_PFC_PIN_GROUP(msiof3_clk_e),
4359 SH_PFC_PIN_GROUP(msiof3_sync_e),
4360 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4361 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4362 SH_PFC_PIN_GROUP(msiof3_txd_e),
4363 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4364 SH_PFC_PIN_GROUP(pwm0),
4365 SH_PFC_PIN_GROUP(pwm1_a),
4366 SH_PFC_PIN_GROUP(pwm1_b),
4367 SH_PFC_PIN_GROUP(pwm2_a),
4368 SH_PFC_PIN_GROUP(pwm2_b),
4369 SH_PFC_PIN_GROUP(pwm3_a),
4370 SH_PFC_PIN_GROUP(pwm3_b),
4371 SH_PFC_PIN_GROUP(pwm4_a),
4372 SH_PFC_PIN_GROUP(pwm4_b),
4373 SH_PFC_PIN_GROUP(pwm5_a),
4374 SH_PFC_PIN_GROUP(pwm5_b),
4375 SH_PFC_PIN_GROUP(pwm6_a),
4376 SH_PFC_PIN_GROUP(pwm6_b),
4377 SH_PFC_PIN_GROUP(sata0_devslp_a),
4378 SH_PFC_PIN_GROUP(sata0_devslp_b),
4379 SH_PFC_PIN_GROUP(scif0_data),
4380 SH_PFC_PIN_GROUP(scif0_clk),
4381 SH_PFC_PIN_GROUP(scif0_ctrl),
4382 SH_PFC_PIN_GROUP(scif1_data_a),
4383 SH_PFC_PIN_GROUP(scif1_clk),
4384 SH_PFC_PIN_GROUP(scif1_ctrl),
4385 SH_PFC_PIN_GROUP(scif1_data_b),
4386 SH_PFC_PIN_GROUP(scif2_data_a),
4387 SH_PFC_PIN_GROUP(scif2_clk),
4388 SH_PFC_PIN_GROUP(scif2_data_b),
4389 SH_PFC_PIN_GROUP(scif3_data_a),
4390 SH_PFC_PIN_GROUP(scif3_clk),
4391 SH_PFC_PIN_GROUP(scif3_ctrl),
4392 SH_PFC_PIN_GROUP(scif3_data_b),
4393 SH_PFC_PIN_GROUP(scif4_data_a),
4394 SH_PFC_PIN_GROUP(scif4_clk_a),
4395 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4396 SH_PFC_PIN_GROUP(scif4_data_b),
4397 SH_PFC_PIN_GROUP(scif4_clk_b),
4398 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4399 SH_PFC_PIN_GROUP(scif4_data_c),
4400 SH_PFC_PIN_GROUP(scif4_clk_c),
4401 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4402 SH_PFC_PIN_GROUP(scif5_data_a),
4403 SH_PFC_PIN_GROUP(scif5_clk_a),
4404 SH_PFC_PIN_GROUP(scif5_data_b),
4405 SH_PFC_PIN_GROUP(scif5_clk_b),
4406 SH_PFC_PIN_GROUP(scif_clk_a),
4407 SH_PFC_PIN_GROUP(scif_clk_b),
4408 SH_PFC_PIN_GROUP(sdhi0_data1),
4409 SH_PFC_PIN_GROUP(sdhi0_data4),
4410 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4411 SH_PFC_PIN_GROUP(sdhi0_cd),
4412 SH_PFC_PIN_GROUP(sdhi0_wp),
4413 SH_PFC_PIN_GROUP(sdhi1_data1),
4414 SH_PFC_PIN_GROUP(sdhi1_data4),
4415 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4416 SH_PFC_PIN_GROUP(sdhi1_cd),
4417 SH_PFC_PIN_GROUP(sdhi1_wp),
4418 SH_PFC_PIN_GROUP(sdhi2_data1),
4419 SH_PFC_PIN_GROUP(sdhi2_data4),
4420 SH_PFC_PIN_GROUP(sdhi2_data8),
4421 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4422 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4423 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4424 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4425 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4426 SH_PFC_PIN_GROUP(sdhi2_ds),
4427 SH_PFC_PIN_GROUP(sdhi3_data1),
4428 SH_PFC_PIN_GROUP(sdhi3_data4),
4429 SH_PFC_PIN_GROUP(sdhi3_data8),
4430 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4431 SH_PFC_PIN_GROUP(sdhi3_cd),
4432 SH_PFC_PIN_GROUP(sdhi3_wp),
4433 SH_PFC_PIN_GROUP(sdhi3_ds),
4434 SH_PFC_PIN_GROUP(ssi0_data),
4435 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4436 SH_PFC_PIN_GROUP(ssi1_data_a),
4437 SH_PFC_PIN_GROUP(ssi1_data_b),
4438 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4439 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4440 SH_PFC_PIN_GROUP(ssi2_data_a),
4441 SH_PFC_PIN_GROUP(ssi2_data_b),
4442 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4443 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4444 SH_PFC_PIN_GROUP(ssi3_data),
4445 SH_PFC_PIN_GROUP(ssi349_ctrl),
4446 SH_PFC_PIN_GROUP(ssi4_data),
4447 SH_PFC_PIN_GROUP(ssi4_ctrl),
4448 SH_PFC_PIN_GROUP(ssi5_data),
4449 SH_PFC_PIN_GROUP(ssi5_ctrl),
4450 SH_PFC_PIN_GROUP(ssi6_data),
4451 SH_PFC_PIN_GROUP(ssi6_ctrl),
4452 SH_PFC_PIN_GROUP(ssi7_data),
4453 SH_PFC_PIN_GROUP(ssi78_ctrl),
4454 SH_PFC_PIN_GROUP(ssi8_data),
4455 SH_PFC_PIN_GROUP(ssi9_data_a),
4456 SH_PFC_PIN_GROUP(ssi9_data_b),
4457 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4458 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4459 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4460 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4461 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4462 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4463 SH_PFC_PIN_GROUP(tpu_to0),
4464 SH_PFC_PIN_GROUP(tpu_to1),
4465 SH_PFC_PIN_GROUP(tpu_to2),
4466 SH_PFC_PIN_GROUP(tpu_to3),
4467 SH_PFC_PIN_GROUP(usb0),
4468 SH_PFC_PIN_GROUP(usb1),
4469 SH_PFC_PIN_GROUP(usb2),
4470 SH_PFC_PIN_GROUP(usb2_ch3),
4471 SH_PFC_PIN_GROUP(usb30),
4472 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4473 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4474 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4475 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4476 SH_PFC_PIN_GROUP(vin4_data18_a),
4477 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4478 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4479 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4480 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4481 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4482 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4483 SH_PFC_PIN_GROUP(vin4_data18_b),
4484 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4485 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4486 SH_PFC_PIN_GROUP(vin4_sync),
4487 SH_PFC_PIN_GROUP(vin4_field),
4488 SH_PFC_PIN_GROUP(vin4_clkenb),
4489 SH_PFC_PIN_GROUP(vin4_clk),
4490 VIN_DATA_PIN_GROUP(vin5_data, 8),
4491 VIN_DATA_PIN_GROUP(vin5_data, 10),
4492 VIN_DATA_PIN_GROUP(vin5_data, 12),
4493 VIN_DATA_PIN_GROUP(vin5_data, 16),
4494 SH_PFC_PIN_GROUP(vin5_sync),
4495 SH_PFC_PIN_GROUP(vin5_field),
4496 SH_PFC_PIN_GROUP(vin5_clkenb),
4497 SH_PFC_PIN_GROUP(vin5_clk),
4498 },
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4499#ifdef CONFIG_PINCTRL_PFC_R8A7795
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4500 .automotive = {
4501 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4502 SH_PFC_PIN_GROUP(drif0_data0_a),
4503 SH_PFC_PIN_GROUP(drif0_data1_a),
4504 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4505 SH_PFC_PIN_GROUP(drif0_data0_b),
4506 SH_PFC_PIN_GROUP(drif0_data1_b),
4507 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4508 SH_PFC_PIN_GROUP(drif0_data0_c),
4509 SH_PFC_PIN_GROUP(drif0_data1_c),
4510 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4511 SH_PFC_PIN_GROUP(drif1_data0_a),
4512 SH_PFC_PIN_GROUP(drif1_data1_a),
4513 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4514 SH_PFC_PIN_GROUP(drif1_data0_b),
4515 SH_PFC_PIN_GROUP(drif1_data1_b),
4516 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4517 SH_PFC_PIN_GROUP(drif1_data0_c),
4518 SH_PFC_PIN_GROUP(drif1_data1_c),
4519 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4520 SH_PFC_PIN_GROUP(drif2_data0_a),
4521 SH_PFC_PIN_GROUP(drif2_data1_a),
4522 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4523 SH_PFC_PIN_GROUP(drif2_data0_b),
4524 SH_PFC_PIN_GROUP(drif2_data1_b),
4525 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4526 SH_PFC_PIN_GROUP(drif3_data0_a),
4527 SH_PFC_PIN_GROUP(drif3_data1_a),
4528 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4529 SH_PFC_PIN_GROUP(drif3_data0_b),
4530 SH_PFC_PIN_GROUP(drif3_data1_b),
4531 }
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4532#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4533};
4534
4535static const char * const audio_clk_groups[] = {
4536 "audio_clk_a_a",
4537 "audio_clk_a_b",
4538 "audio_clk_a_c",
4539 "audio_clk_b_a",
4540 "audio_clk_b_b",
4541 "audio_clk_c_a",
4542 "audio_clk_c_b",
4543 "audio_clkout_a",
4544 "audio_clkout_b",
4545 "audio_clkout_c",
4546 "audio_clkout_d",
4547 "audio_clkout1_a",
4548 "audio_clkout1_b",
4549 "audio_clkout2_a",
4550 "audio_clkout2_b",
4551 "audio_clkout3_a",
4552 "audio_clkout3_b",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4553};
4554
4555static const char * const avb_groups[] = {
4556 "avb_link",
4557 "avb_magic",
4558 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4559 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4560 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4561 "avb_mii",
4562 "avb_avtp_pps",
4563 "avb_avtp_match_a",
4564 "avb_avtp_capture_a",
4565 "avb_avtp_match_b",
4566 "avb_avtp_capture_b",
4567};
4568
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4569static const char * const can0_groups[] = {
4570 "can0_data_a",
4571 "can0_data_b",
4572};
4573
4574static const char * const can1_groups[] = {
4575 "can1_data",
4576};
4577
4578static const char * const can_clk_groups[] = {
4579 "can_clk",
4580};
4581
4582static const char * const canfd0_groups[] = {
4583 "canfd0_data_a",
4584 "canfd0_data_b",
4585};
4586
4587static const char * const canfd1_groups[] = {
4588 "canfd1_data",
4589};
4590
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4591#ifdef CONFIG_PINCTRL_PFC_R8A7795
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4592static const char * const drif0_groups[] = {
4593 "drif0_ctrl_a",
4594 "drif0_data0_a",
4595 "drif0_data1_a",
4596 "drif0_ctrl_b",
4597 "drif0_data0_b",
4598 "drif0_data1_b",
4599 "drif0_ctrl_c",
4600 "drif0_data0_c",
4601 "drif0_data1_c",
4602};
4603
4604static const char * const drif1_groups[] = {
4605 "drif1_ctrl_a",
4606 "drif1_data0_a",
4607 "drif1_data1_a",
4608 "drif1_ctrl_b",
4609 "drif1_data0_b",
4610 "drif1_data1_b",
4611 "drif1_ctrl_c",
4612 "drif1_data0_c",
4613 "drif1_data1_c",
4614};
4615
4616static const char * const drif2_groups[] = {
4617 "drif2_ctrl_a",
4618 "drif2_data0_a",
4619 "drif2_data1_a",
4620 "drif2_ctrl_b",
4621 "drif2_data0_b",
4622 "drif2_data1_b",
4623};
4624
4625static const char * const drif3_groups[] = {
4626 "drif3_ctrl_a",
4627 "drif3_data0_a",
4628 "drif3_data1_a",
4629 "drif3_ctrl_b",
4630 "drif3_data0_b",
4631 "drif3_data1_b",
4632};
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4633#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4634
4635static const char * const du_groups[] = {
4636 "du_rgb666",
4637 "du_rgb888",
4638 "du_clk_out_0",
4639 "du_clk_out_1",
4640 "du_sync",
4641 "du_oddf",
4642 "du_cde",
4643 "du_disp",
4644};
4645
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4646static const char * const hscif0_groups[] = {
4647 "hscif0_data",
4648 "hscif0_clk",
4649 "hscif0_ctrl",
4650};
4651
4652static const char * const hscif1_groups[] = {
4653 "hscif1_data_a",
4654 "hscif1_clk_a",
4655 "hscif1_ctrl_a",
4656 "hscif1_data_b",
4657 "hscif1_clk_b",
4658 "hscif1_ctrl_b",
4659};
4660
4661static const char * const hscif2_groups[] = {
4662 "hscif2_data_a",
4663 "hscif2_clk_a",
4664 "hscif2_ctrl_a",
4665 "hscif2_data_b",
4666 "hscif2_clk_b",
4667 "hscif2_ctrl_b",
4668 "hscif2_data_c",
4669 "hscif2_clk_c",
4670 "hscif2_ctrl_c",
4671};
4672
4673static const char * const hscif3_groups[] = {
4674 "hscif3_data_a",
4675 "hscif3_clk",
4676 "hscif3_ctrl",
4677 "hscif3_data_b",
4678 "hscif3_data_c",
4679 "hscif3_data_d",
4680};
4681
4682static const char * const hscif4_groups[] = {
4683 "hscif4_data_a",
4684 "hscif4_clk",
4685 "hscif4_ctrl",
4686 "hscif4_data_b",
4687};
4688
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4689static const char * const i2c0_groups[] = {
4690 "i2c0",
4691};
4692
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4693static const char * const i2c1_groups[] = {
4694 "i2c1_a",
4695 "i2c1_b",
4696};
4697
4698static const char * const i2c2_groups[] = {
4699 "i2c2_a",
4700 "i2c2_b",
4701};
4702
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4703static const char * const i2c3_groups[] = {
4704 "i2c3",
4705};
4706
4707static const char * const i2c5_groups[] = {
4708 "i2c5",
4709};
4710
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4711static const char * const i2c6_groups[] = {
4712 "i2c6_a",
4713 "i2c6_b",
4714 "i2c6_c",
4715};
4716
4717static const char * const intc_ex_groups[] = {
4718 "intc_ex_irq0",
4719 "intc_ex_irq1",
4720 "intc_ex_irq2",
4721 "intc_ex_irq3",
4722 "intc_ex_irq4",
4723 "intc_ex_irq5",
4724};
4725
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4726static const char * const msiof0_groups[] = {
4727 "msiof0_clk",
4728 "msiof0_sync",
4729 "msiof0_ss1",
4730 "msiof0_ss2",
4731 "msiof0_txd",
4732 "msiof0_rxd",
4733};
4734
4735static const char * const msiof1_groups[] = {
4736 "msiof1_clk_a",
4737 "msiof1_sync_a",
4738 "msiof1_ss1_a",
4739 "msiof1_ss2_a",
4740 "msiof1_txd_a",
4741 "msiof1_rxd_a",
4742 "msiof1_clk_b",
4743 "msiof1_sync_b",
4744 "msiof1_ss1_b",
4745 "msiof1_ss2_b",
4746 "msiof1_txd_b",
4747 "msiof1_rxd_b",
4748 "msiof1_clk_c",
4749 "msiof1_sync_c",
4750 "msiof1_ss1_c",
4751 "msiof1_ss2_c",
4752 "msiof1_txd_c",
4753 "msiof1_rxd_c",
4754 "msiof1_clk_d",
4755 "msiof1_sync_d",
4756 "msiof1_ss1_d",
4757 "msiof1_ss2_d",
4758 "msiof1_txd_d",
4759 "msiof1_rxd_d",
4760 "msiof1_clk_e",
4761 "msiof1_sync_e",
4762 "msiof1_ss1_e",
4763 "msiof1_ss2_e",
4764 "msiof1_txd_e",
4765 "msiof1_rxd_e",
4766 "msiof1_clk_f",
4767 "msiof1_sync_f",
4768 "msiof1_ss1_f",
4769 "msiof1_ss2_f",
4770 "msiof1_txd_f",
4771 "msiof1_rxd_f",
4772 "msiof1_clk_g",
4773 "msiof1_sync_g",
4774 "msiof1_ss1_g",
4775 "msiof1_ss2_g",
4776 "msiof1_txd_g",
4777 "msiof1_rxd_g",
4778};
4779
4780static const char * const msiof2_groups[] = {
4781 "msiof2_clk_a",
4782 "msiof2_sync_a",
4783 "msiof2_ss1_a",
4784 "msiof2_ss2_a",
4785 "msiof2_txd_a",
4786 "msiof2_rxd_a",
4787 "msiof2_clk_b",
4788 "msiof2_sync_b",
4789 "msiof2_ss1_b",
4790 "msiof2_ss2_b",
4791 "msiof2_txd_b",
4792 "msiof2_rxd_b",
4793 "msiof2_clk_c",
4794 "msiof2_sync_c",
4795 "msiof2_ss1_c",
4796 "msiof2_ss2_c",
4797 "msiof2_txd_c",
4798 "msiof2_rxd_c",
4799 "msiof2_clk_d",
4800 "msiof2_sync_d",
4801 "msiof2_ss1_d",
4802 "msiof2_ss2_d",
4803 "msiof2_txd_d",
4804 "msiof2_rxd_d",
4805};
4806
4807static const char * const msiof3_groups[] = {
4808 "msiof3_clk_a",
4809 "msiof3_sync_a",
4810 "msiof3_ss1_a",
4811 "msiof3_ss2_a",
4812 "msiof3_txd_a",
4813 "msiof3_rxd_a",
4814 "msiof3_clk_b",
4815 "msiof3_sync_b",
4816 "msiof3_ss1_b",
4817 "msiof3_ss2_b",
4818 "msiof3_txd_b",
4819 "msiof3_rxd_b",
4820 "msiof3_clk_c",
4821 "msiof3_sync_c",
4822 "msiof3_txd_c",
4823 "msiof3_rxd_c",
4824 "msiof3_clk_d",
4825 "msiof3_sync_d",
4826 "msiof3_ss1_d",
4827 "msiof3_txd_d",
4828 "msiof3_rxd_d",
4829 "msiof3_clk_e",
4830 "msiof3_sync_e",
4831 "msiof3_ss1_e",
4832 "msiof3_ss2_e",
4833 "msiof3_txd_e",
4834 "msiof3_rxd_e",
4835};
4836
4837static const char * const pwm0_groups[] = {
4838 "pwm0",
4839};
4840
4841static const char * const pwm1_groups[] = {
4842 "pwm1_a",
4843 "pwm1_b",
4844};
4845
4846static const char * const pwm2_groups[] = {
4847 "pwm2_a",
4848 "pwm2_b",
4849};
4850
4851static const char * const pwm3_groups[] = {
4852 "pwm3_a",
4853 "pwm3_b",
4854};
4855
4856static const char * const pwm4_groups[] = {
4857 "pwm4_a",
4858 "pwm4_b",
4859};
4860
4861static const char * const pwm5_groups[] = {
4862 "pwm5_a",
4863 "pwm5_b",
4864};
4865
4866static const char * const pwm6_groups[] = {
4867 "pwm6_a",
4868 "pwm6_b",
4869};
4870
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4871static const char * const sata0_groups[] = {
4872 "sata0_devslp_a",
4873 "sata0_devslp_b",
4874};
4875
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4876static const char * const scif0_groups[] = {
4877 "scif0_data",
4878 "scif0_clk",
4879 "scif0_ctrl",
4880};
4881
4882static const char * const scif1_groups[] = {
4883 "scif1_data_a",
4884 "scif1_clk",
4885 "scif1_ctrl",
4886 "scif1_data_b",
4887};
4888
4889static const char * const scif2_groups[] = {
4890 "scif2_data_a",
4891 "scif2_clk",
4892 "scif2_data_b",
4893};
4894
4895static const char * const scif3_groups[] = {
4896 "scif3_data_a",
4897 "scif3_clk",
4898 "scif3_ctrl",
4899 "scif3_data_b",
4900};
4901
4902static const char * const scif4_groups[] = {
4903 "scif4_data_a",
4904 "scif4_clk_a",
4905 "scif4_ctrl_a",
4906 "scif4_data_b",
4907 "scif4_clk_b",
4908 "scif4_ctrl_b",
4909 "scif4_data_c",
4910 "scif4_clk_c",
4911 "scif4_ctrl_c",
4912};
4913
4914static const char * const scif5_groups[] = {
4915 "scif5_data_a",
4916 "scif5_clk_a",
4917 "scif5_data_b",
4918 "scif5_clk_b",
4919};
4920
4921static const char * const scif_clk_groups[] = {
4922 "scif_clk_a",
4923 "scif_clk_b",
4924};
4925
4926static const char * const sdhi0_groups[] = {
4927 "sdhi0_data1",
4928 "sdhi0_data4",
4929 "sdhi0_ctrl",
4930 "sdhi0_cd",
4931 "sdhi0_wp",
4932};
4933
4934static const char * const sdhi1_groups[] = {
4935 "sdhi1_data1",
4936 "sdhi1_data4",
4937 "sdhi1_ctrl",
4938 "sdhi1_cd",
4939 "sdhi1_wp",
4940};
4941
4942static const char * const sdhi2_groups[] = {
4943 "sdhi2_data1",
4944 "sdhi2_data4",
4945 "sdhi2_data8",
4946 "sdhi2_ctrl",
4947 "sdhi2_cd_a",
4948 "sdhi2_wp_a",
4949 "sdhi2_cd_b",
4950 "sdhi2_wp_b",
4951 "sdhi2_ds",
4952};
4953
4954static const char * const sdhi3_groups[] = {
4955 "sdhi3_data1",
4956 "sdhi3_data4",
4957 "sdhi3_data8",
4958 "sdhi3_ctrl",
4959 "sdhi3_cd",
4960 "sdhi3_wp",
4961 "sdhi3_ds",
4962};
4963
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4964static const char * const ssi_groups[] = {
4965 "ssi0_data",
4966 "ssi01239_ctrl",
4967 "ssi1_data_a",
4968 "ssi1_data_b",
4969 "ssi1_ctrl_a",
4970 "ssi1_ctrl_b",
4971 "ssi2_data_a",
4972 "ssi2_data_b",
4973 "ssi2_ctrl_a",
4974 "ssi2_ctrl_b",
4975 "ssi3_data",
4976 "ssi349_ctrl",
4977 "ssi4_data",
4978 "ssi4_ctrl",
4979 "ssi5_data",
4980 "ssi5_ctrl",
4981 "ssi6_data",
4982 "ssi6_ctrl",
4983 "ssi7_data",
4984 "ssi78_ctrl",
4985 "ssi8_data",
4986 "ssi9_data_a",
4987 "ssi9_data_b",
4988 "ssi9_ctrl_a",
4989 "ssi9_ctrl_b",
4990};
4991
4992static const char * const tmu_groups[] = {
4993 "tmu_tclk1_a",
4994 "tmu_tclk1_b",
4995 "tmu_tclk2_a",
4996 "tmu_tclk2_b",
4997};
4998
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4999static const char * const tpu_groups[] = {
5000 "tpu_to0",
5001 "tpu_to1",
5002 "tpu_to2",
5003 "tpu_to3",
5004};
5005
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5006static const char * const usb0_groups[] = {
5007 "usb0",
5008};
5009
5010static const char * const usb1_groups[] = {
5011 "usb1",
5012};
5013
5014static const char * const usb2_groups[] = {
5015 "usb2",
5016};
5017
5018static const char * const usb2_ch3_groups[] = {
5019 "usb2_ch3",
5020};
5021
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5022static const char * const usb30_groups[] = {
5023 "usb30",
5024};
5025
5026static const char * const vin4_groups[] = {
5027 "vin4_data8_a",
5028 "vin4_data10_a",
5029 "vin4_data12_a",
5030 "vin4_data16_a",
5031 "vin4_data18_a",
5032 "vin4_data20_a",
5033 "vin4_data24_a",
5034 "vin4_data8_b",
5035 "vin4_data10_b",
5036 "vin4_data12_b",
5037 "vin4_data16_b",
5038 "vin4_data18_b",
5039 "vin4_data20_b",
5040 "vin4_data24_b",
5041 "vin4_sync",
5042 "vin4_field",
5043 "vin4_clkenb",
5044 "vin4_clk",
5045};
5046
5047static const char * const vin5_groups[] = {
5048 "vin5_data8",
5049 "vin5_data10",
5050 "vin5_data12",
5051 "vin5_data16",
5052 "vin5_sync",
5053 "vin5_field",
5054 "vin5_clkenb",
5055 "vin5_clk",
5056};
5057
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5058static const struct {
5059 struct sh_pfc_function common[53];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5060#ifdef CONFIG_PINCTRL_PFC_R8A7795
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5061 struct sh_pfc_function automotive[4];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5062#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5063} pinmux_functions = {
5064 .common = {
5065 SH_PFC_FUNCTION(audio_clk),
5066 SH_PFC_FUNCTION(avb),
5067 SH_PFC_FUNCTION(can0),
5068 SH_PFC_FUNCTION(can1),
5069 SH_PFC_FUNCTION(can_clk),
5070 SH_PFC_FUNCTION(canfd0),
5071 SH_PFC_FUNCTION(canfd1),
5072 SH_PFC_FUNCTION(du),
5073 SH_PFC_FUNCTION(hscif0),
5074 SH_PFC_FUNCTION(hscif1),
5075 SH_PFC_FUNCTION(hscif2),
5076 SH_PFC_FUNCTION(hscif3),
5077 SH_PFC_FUNCTION(hscif4),
5078 SH_PFC_FUNCTION(i2c0),
5079 SH_PFC_FUNCTION(i2c1),
5080 SH_PFC_FUNCTION(i2c2),
5081 SH_PFC_FUNCTION(i2c3),
5082 SH_PFC_FUNCTION(i2c5),
5083 SH_PFC_FUNCTION(i2c6),
5084 SH_PFC_FUNCTION(intc_ex),
5085 SH_PFC_FUNCTION(msiof0),
5086 SH_PFC_FUNCTION(msiof1),
5087 SH_PFC_FUNCTION(msiof2),
5088 SH_PFC_FUNCTION(msiof3),
5089 SH_PFC_FUNCTION(pwm0),
5090 SH_PFC_FUNCTION(pwm1),
5091 SH_PFC_FUNCTION(pwm2),
5092 SH_PFC_FUNCTION(pwm3),
5093 SH_PFC_FUNCTION(pwm4),
5094 SH_PFC_FUNCTION(pwm5),
5095 SH_PFC_FUNCTION(pwm6),
5096 SH_PFC_FUNCTION(sata0),
5097 SH_PFC_FUNCTION(scif0),
5098 SH_PFC_FUNCTION(scif1),
5099 SH_PFC_FUNCTION(scif2),
5100 SH_PFC_FUNCTION(scif3),
5101 SH_PFC_FUNCTION(scif4),
5102 SH_PFC_FUNCTION(scif5),
5103 SH_PFC_FUNCTION(scif_clk),
5104 SH_PFC_FUNCTION(sdhi0),
5105 SH_PFC_FUNCTION(sdhi1),
5106 SH_PFC_FUNCTION(sdhi2),
5107 SH_PFC_FUNCTION(sdhi3),
5108 SH_PFC_FUNCTION(ssi),
5109 SH_PFC_FUNCTION(tmu),
5110 SH_PFC_FUNCTION(tpu),
5111 SH_PFC_FUNCTION(usb0),
5112 SH_PFC_FUNCTION(usb1),
5113 SH_PFC_FUNCTION(usb2),
5114 SH_PFC_FUNCTION(usb2_ch3),
5115 SH_PFC_FUNCTION(usb30),
5116 SH_PFC_FUNCTION(vin4),
5117 SH_PFC_FUNCTION(vin5),
5118 },
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5119#ifdef CONFIG_PINCTRL_PFC_R8A7795
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5120 .automotive = {
5121 SH_PFC_FUNCTION(drif0),
5122 SH_PFC_FUNCTION(drif1),
5123 SH_PFC_FUNCTION(drif2),
5124 SH_PFC_FUNCTION(drif3),
5125 }
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5126#endif /* CONFIG_PINCTRL_PFC_R8A7795 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5127};
5128
5129static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5130#define F_(x, y) FN_##y
5131#define FM(x) FN_##x
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5132 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5133 0, 0,
5134 0, 0,
5135 0, 0,
5136 0, 0,
5137 0, 0,
5138 0, 0,
5139 0, 0,
5140 0, 0,
5141 0, 0,
5142 0, 0,
5143 0, 0,
5144 0, 0,
5145 0, 0,
5146 0, 0,
5147 0, 0,
5148 0, 0,
5149 GP_0_15_FN, GPSR0_15,
5150 GP_0_14_FN, GPSR0_14,
5151 GP_0_13_FN, GPSR0_13,
5152 GP_0_12_FN, GPSR0_12,
5153 GP_0_11_FN, GPSR0_11,
5154 GP_0_10_FN, GPSR0_10,
5155 GP_0_9_FN, GPSR0_9,
5156 GP_0_8_FN, GPSR0_8,
5157 GP_0_7_FN, GPSR0_7,
5158 GP_0_6_FN, GPSR0_6,
5159 GP_0_5_FN, GPSR0_5,
5160 GP_0_4_FN, GPSR0_4,
5161 GP_0_3_FN, GPSR0_3,
5162 GP_0_2_FN, GPSR0_2,
5163 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5164 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5165 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5166 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5167 0, 0,
5168 0, 0,
5169 0, 0,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5170 GP_1_28_FN, GPSR1_28,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5171 GP_1_27_FN, GPSR1_27,
5172 GP_1_26_FN, GPSR1_26,
5173 GP_1_25_FN, GPSR1_25,
5174 GP_1_24_FN, GPSR1_24,
5175 GP_1_23_FN, GPSR1_23,
5176 GP_1_22_FN, GPSR1_22,
5177 GP_1_21_FN, GPSR1_21,
5178 GP_1_20_FN, GPSR1_20,
5179 GP_1_19_FN, GPSR1_19,
5180 GP_1_18_FN, GPSR1_18,
5181 GP_1_17_FN, GPSR1_17,
5182 GP_1_16_FN, GPSR1_16,
5183 GP_1_15_FN, GPSR1_15,
5184 GP_1_14_FN, GPSR1_14,
5185 GP_1_13_FN, GPSR1_13,
5186 GP_1_12_FN, GPSR1_12,
5187 GP_1_11_FN, GPSR1_11,
5188 GP_1_10_FN, GPSR1_10,
5189 GP_1_9_FN, GPSR1_9,
5190 GP_1_8_FN, GPSR1_8,
5191 GP_1_7_FN, GPSR1_7,
5192 GP_1_6_FN, GPSR1_6,
5193 GP_1_5_FN, GPSR1_5,
5194 GP_1_4_FN, GPSR1_4,
5195 GP_1_3_FN, GPSR1_3,
5196 GP_1_2_FN, GPSR1_2,
5197 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5198 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5199 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5200 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5201 0, 0,
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 0, 0,
5209 0, 0,
5210 0, 0,
5211 0, 0,
5212 0, 0,
5213 0, 0,
5214 0, 0,
5215 0, 0,
5216 0, 0,
5217 0, 0,
5218 GP_2_14_FN, GPSR2_14,
5219 GP_2_13_FN, GPSR2_13,
5220 GP_2_12_FN, GPSR2_12,
5221 GP_2_11_FN, GPSR2_11,
5222 GP_2_10_FN, GPSR2_10,
5223 GP_2_9_FN, GPSR2_9,
5224 GP_2_8_FN, GPSR2_8,
5225 GP_2_7_FN, GPSR2_7,
5226 GP_2_6_FN, GPSR2_6,
5227 GP_2_5_FN, GPSR2_5,
5228 GP_2_4_FN, GPSR2_4,
5229 GP_2_3_FN, GPSR2_3,
5230 GP_2_2_FN, GPSR2_2,
5231 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5232 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5233 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5234 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5235 0, 0,
5236 0, 0,
5237 0, 0,
5238 0, 0,
5239 0, 0,
5240 0, 0,
5241 0, 0,
5242 0, 0,
5243 0, 0,
5244 0, 0,
5245 0, 0,
5246 0, 0,
5247 0, 0,
5248 0, 0,
5249 0, 0,
5250 0, 0,
5251 GP_3_15_FN, GPSR3_15,
5252 GP_3_14_FN, GPSR3_14,
5253 GP_3_13_FN, GPSR3_13,
5254 GP_3_12_FN, GPSR3_12,
5255 GP_3_11_FN, GPSR3_11,
5256 GP_3_10_FN, GPSR3_10,
5257 GP_3_9_FN, GPSR3_9,
5258 GP_3_8_FN, GPSR3_8,
5259 GP_3_7_FN, GPSR3_7,
5260 GP_3_6_FN, GPSR3_6,
5261 GP_3_5_FN, GPSR3_5,
5262 GP_3_4_FN, GPSR3_4,
5263 GP_3_3_FN, GPSR3_3,
5264 GP_3_2_FN, GPSR3_2,
5265 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5266 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5267 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5268 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5269 0, 0,
5270 0, 0,
5271 0, 0,
5272 0, 0,
5273 0, 0,
5274 0, 0,
5275 0, 0,
5276 0, 0,
5277 0, 0,
5278 0, 0,
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 GP_4_17_FN, GPSR4_17,
5284 GP_4_16_FN, GPSR4_16,
5285 GP_4_15_FN, GPSR4_15,
5286 GP_4_14_FN, GPSR4_14,
5287 GP_4_13_FN, GPSR4_13,
5288 GP_4_12_FN, GPSR4_12,
5289 GP_4_11_FN, GPSR4_11,
5290 GP_4_10_FN, GPSR4_10,
5291 GP_4_9_FN, GPSR4_9,
5292 GP_4_8_FN, GPSR4_8,
5293 GP_4_7_FN, GPSR4_7,
5294 GP_4_6_FN, GPSR4_6,
5295 GP_4_5_FN, GPSR4_5,
5296 GP_4_4_FN, GPSR4_4,
5297 GP_4_3_FN, GPSR4_3,
5298 GP_4_2_FN, GPSR4_2,
5299 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5300 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5301 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5302 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5303 0, 0,
5304 0, 0,
5305 0, 0,
5306 0, 0,
5307 0, 0,
5308 0, 0,
5309 GP_5_25_FN, GPSR5_25,
5310 GP_5_24_FN, GPSR5_24,
5311 GP_5_23_FN, GPSR5_23,
5312 GP_5_22_FN, GPSR5_22,
5313 GP_5_21_FN, GPSR5_21,
5314 GP_5_20_FN, GPSR5_20,
5315 GP_5_19_FN, GPSR5_19,
5316 GP_5_18_FN, GPSR5_18,
5317 GP_5_17_FN, GPSR5_17,
5318 GP_5_16_FN, GPSR5_16,
5319 GP_5_15_FN, GPSR5_15,
5320 GP_5_14_FN, GPSR5_14,
5321 GP_5_13_FN, GPSR5_13,
5322 GP_5_12_FN, GPSR5_12,
5323 GP_5_11_FN, GPSR5_11,
5324 GP_5_10_FN, GPSR5_10,
5325 GP_5_9_FN, GPSR5_9,
5326 GP_5_8_FN, GPSR5_8,
5327 GP_5_7_FN, GPSR5_7,
5328 GP_5_6_FN, GPSR5_6,
5329 GP_5_5_FN, GPSR5_5,
5330 GP_5_4_FN, GPSR5_4,
5331 GP_5_3_FN, GPSR5_3,
5332 GP_5_2_FN, GPSR5_2,
5333 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5334 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5335 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5336 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5337 GP_6_31_FN, GPSR6_31,
5338 GP_6_30_FN, GPSR6_30,
5339 GP_6_29_FN, GPSR6_29,
5340 GP_6_28_FN, GPSR6_28,
5341 GP_6_27_FN, GPSR6_27,
5342 GP_6_26_FN, GPSR6_26,
5343 GP_6_25_FN, GPSR6_25,
5344 GP_6_24_FN, GPSR6_24,
5345 GP_6_23_FN, GPSR6_23,
5346 GP_6_22_FN, GPSR6_22,
5347 GP_6_21_FN, GPSR6_21,
5348 GP_6_20_FN, GPSR6_20,
5349 GP_6_19_FN, GPSR6_19,
5350 GP_6_18_FN, GPSR6_18,
5351 GP_6_17_FN, GPSR6_17,
5352 GP_6_16_FN, GPSR6_16,
5353 GP_6_15_FN, GPSR6_15,
5354 GP_6_14_FN, GPSR6_14,
5355 GP_6_13_FN, GPSR6_13,
5356 GP_6_12_FN, GPSR6_12,
5357 GP_6_11_FN, GPSR6_11,
5358 GP_6_10_FN, GPSR6_10,
5359 GP_6_9_FN, GPSR6_9,
5360 GP_6_8_FN, GPSR6_8,
5361 GP_6_7_FN, GPSR6_7,
5362 GP_6_6_FN, GPSR6_6,
5363 GP_6_5_FN, GPSR6_5,
5364 GP_6_4_FN, GPSR6_4,
5365 GP_6_3_FN, GPSR6_3,
5366 GP_6_2_FN, GPSR6_2,
5367 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5368 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5369 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5370 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5371 0, 0,
5372 0, 0,
5373 0, 0,
5374 0, 0,
5375 0, 0,
5376 0, 0,
5377 0, 0,
5378 0, 0,
5379 0, 0,
5380 0, 0,
5381 0, 0,
5382 0, 0,
5383 0, 0,
5384 0, 0,
5385 0, 0,
5386 0, 0,
5387 0, 0,
5388 0, 0,
5389 0, 0,
5390 0, 0,
5391 0, 0,
5392 0, 0,
5393 0, 0,
5394 0, 0,
5395 0, 0,
5396 0, 0,
5397 0, 0,
5398 0, 0,
5399 GP_7_3_FN, GPSR7_3,
5400 GP_7_2_FN, GPSR7_2,
5401 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5402 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5403 },
5404#undef F_
5405#undef FM
5406
5407#define F_(x, y) x,
5408#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5409 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5410 IP0_31_28
5411 IP0_27_24
5412 IP0_23_20
5413 IP0_19_16
5414 IP0_15_12
5415 IP0_11_8
5416 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5417 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5418 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5419 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5420 IP1_31_28
5421 IP1_27_24
5422 IP1_23_20
5423 IP1_19_16
5424 IP1_15_12
5425 IP1_11_8
5426 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5427 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5428 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5429 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5430 IP2_31_28
5431 IP2_27_24
5432 IP2_23_20
5433 IP2_19_16
5434 IP2_15_12
5435 IP2_11_8
5436 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5437 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5438 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5439 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5440 IP3_31_28
5441 IP3_27_24
5442 IP3_23_20
5443 IP3_19_16
5444 IP3_15_12
5445 IP3_11_8
5446 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5447 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5448 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5449 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5450 IP4_31_28
5451 IP4_27_24
5452 IP4_23_20
5453 IP4_19_16
5454 IP4_15_12
5455 IP4_11_8
5456 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5457 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5458 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5459 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5460 IP5_31_28
5461 IP5_27_24
5462 IP5_23_20
5463 IP5_19_16
5464 IP5_15_12
5465 IP5_11_8
5466 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5467 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5468 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5469 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5470 IP6_31_28
5471 IP6_27_24
5472 IP6_23_20
5473 IP6_19_16
5474 IP6_15_12
5475 IP6_11_8
5476 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5477 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5478 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5479 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5480 IP7_31_28
5481 IP7_27_24
5482 IP7_23_20
5483 IP7_19_16
5484 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5485 IP7_11_8
5486 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5487 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5488 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5489 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5490 IP8_31_28
5491 IP8_27_24
5492 IP8_23_20
5493 IP8_19_16
5494 IP8_15_12
5495 IP8_11_8
5496 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5497 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5498 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5499 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5500 IP9_31_28
5501 IP9_27_24
5502 IP9_23_20
5503 IP9_19_16
5504 IP9_15_12
5505 IP9_11_8
5506 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5507 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5508 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5509 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5510 IP10_31_28
5511 IP10_27_24
5512 IP10_23_20
5513 IP10_19_16
5514 IP10_15_12
5515 IP10_11_8
5516 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5517 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5518 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5519 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5520 IP11_31_28
5521 IP11_27_24
5522 IP11_23_20
5523 IP11_19_16
5524 IP11_15_12
5525 IP11_11_8
5526 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5527 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5528 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5529 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5530 IP12_31_28
5531 IP12_27_24
5532 IP12_23_20
5533 IP12_19_16
5534 IP12_15_12
5535 IP12_11_8
5536 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5537 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5538 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5539 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5540 IP13_31_28
5541 IP13_27_24
5542 IP13_23_20
5543 IP13_19_16
5544 IP13_15_12
5545 IP13_11_8
5546 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5547 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5548 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5549 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5550 IP14_31_28
5551 IP14_27_24
5552 IP14_23_20
5553 IP14_19_16
5554 IP14_15_12
5555 IP14_11_8
5556 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5557 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5558 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5559 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5560 IP15_31_28
5561 IP15_27_24
5562 IP15_23_20
5563 IP15_19_16
5564 IP15_15_12
5565 IP15_11_8
5566 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5567 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5568 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5569 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5570 IP16_31_28
5571 IP16_27_24
5572 IP16_23_20
5573 IP16_19_16
5574 IP16_15_12
5575 IP16_11_8
5576 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5577 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5578 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5579 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5580 IP17_31_28
5581 IP17_27_24
5582 IP17_23_20
5583 IP17_19_16
5584 IP17_15_12
5585 IP17_11_8
5586 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5587 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5588 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5589 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5590 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5591 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5592 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5593 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5594 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5595 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5596 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5597 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5598 },
5599#undef F_
5600#undef FM
5601
5602#define F_(x, y) x,
5603#define FM(x) FN_##x,
5604 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5605 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5606 1, 1, 1, 2, 2, 1, 2, 3),
5607 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5608 MOD_SEL0_31_30_29
5609 MOD_SEL0_28_27
5610 MOD_SEL0_26_25_24
5611 MOD_SEL0_23
5612 MOD_SEL0_22
5613 MOD_SEL0_21
5614 MOD_SEL0_20
5615 MOD_SEL0_19
5616 MOD_SEL0_18_17
5617 MOD_SEL0_16
5618 0, 0, /* RESERVED 15 */
5619 MOD_SEL0_14_13
5620 MOD_SEL0_12
5621 MOD_SEL0_11
5622 MOD_SEL0_10
5623 MOD_SEL0_9_8
5624 MOD_SEL0_7_6
5625 MOD_SEL0_5
5626 MOD_SEL0_4_3
5627 /* RESERVED 2, 1, 0 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5628 0, 0, 0, 0, 0, 0, 0, 0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5629 },
5630 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5631 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5632 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5633 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5634 MOD_SEL1_31_30
5635 MOD_SEL1_29_28_27
5636 MOD_SEL1_26
5637 MOD_SEL1_25_24
5638 MOD_SEL1_23_22_21
5639 MOD_SEL1_20
5640 MOD_SEL1_19
5641 MOD_SEL1_18_17
5642 MOD_SEL1_16
5643 MOD_SEL1_15_14
5644 MOD_SEL1_13
5645 MOD_SEL1_12
5646 MOD_SEL1_11
5647 MOD_SEL1_10
5648 MOD_SEL1_9
5649 0, 0, 0, 0, /* RESERVED 8, 7 */
5650 MOD_SEL1_6
5651 MOD_SEL1_5
5652 MOD_SEL1_4
5653 MOD_SEL1_3
5654 MOD_SEL1_2
5655 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5656 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5657 },
5658 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5659 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5660 1, 4, 4, 4, 3, 1),
5661 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5662 MOD_SEL2_31
5663 MOD_SEL2_30
5664 MOD_SEL2_29
5665 MOD_SEL2_28_27
5666 MOD_SEL2_26
5667 MOD_SEL2_25_24_23
5668 /* RESERVED 22 */
5669 0, 0,
5670 MOD_SEL2_21
5671 MOD_SEL2_20
5672 MOD_SEL2_19
5673 MOD_SEL2_18
5674 MOD_SEL2_17
5675 /* RESERVED 16 */
5676 0, 0,
5677 /* RESERVED 15, 14, 13, 12 */
5678 0, 0, 0, 0, 0, 0, 0, 0,
5679 0, 0, 0, 0, 0, 0, 0, 0,
5680 /* RESERVED 11, 10, 9, 8 */
5681 0, 0, 0, 0, 0, 0, 0, 0,
5682 0, 0, 0, 0, 0, 0, 0, 0,
5683 /* RESERVED 7, 6, 5, 4 */
5684 0, 0, 0, 0, 0, 0, 0, 0,
5685 0, 0, 0, 0, 0, 0, 0, 0,
5686 /* RESERVED 3, 2, 1 */
5687 0, 0, 0, 0, 0, 0, 0, 0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5688 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5689 },
5690 { },
5691};
5692
5693static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5694 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5695 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5696 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5697 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5698 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5699 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5700 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5701 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5702 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5703 } },
5704 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5705 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5706 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5707 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5708 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5709 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5710 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5711 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5712 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5713 } },
5714 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5715 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5716 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5717 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5718 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5719 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5720 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5721 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5722 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5723 } },
5724 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5725 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5726 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5727 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5728 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5729 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5730 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5731 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5732 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5733 } },
5734 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5735 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5736 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5737 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5738 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5739 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5740 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5741 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5742 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5743 } },
5744 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5745 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5746 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5747 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5748 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5749 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5750 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5751 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5752 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5753 } },
5754 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5755 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5756 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5757 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5758 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5759 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5760 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5761 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5762 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5763 } },
5764 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5765 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5766 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5767 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5768 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5769 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5770 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5771 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5772 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5773 } },
5774 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5775 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5776 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5777 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5778 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5779 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5780 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5781 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5782 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5783 } },
5784 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5785 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5786 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5787 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5788 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5789 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5790 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5791 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5792 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5793 } },
5794 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5795 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5796 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5797 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5798 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5799 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5800 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5801 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5802 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5803 } },
5804 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5805 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5806 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5807 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5808 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5809 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5810 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5811 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5812 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5813 } },
5814 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5815 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5816 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5817 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5818 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5819 } },
5820 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5821 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5822 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5823 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5824 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5825 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5826 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5827 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5828 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5829 } },
5830 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5831 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5832 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5833 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5834 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5835 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5836 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5837 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5838 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5839 } },
5840 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5841 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5842 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5843 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5844 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5845 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5846 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5847 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5848 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5849 } },
5850 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5851 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5852 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5853 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5854 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5855 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5856 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5857 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5858 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5859 } },
5860 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5861 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5862 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5863 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5864 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5865 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5866 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5867 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5868 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5869 } },
5870 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5871 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5872 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5873 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5874 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5875 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5876 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5877 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5878 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5879 } },
5880 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5881 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5882 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5883 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5884 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5885 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5886 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5887 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5888 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5889 } },
5890 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5891 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5892 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5893 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5894 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5895 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5896 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5897 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5898 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5899 } },
5900 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5901 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5902 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5903 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5904 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5905 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5906 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5907 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5908 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5909 } },
5910 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5911 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5912 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5913 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5914 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5915 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5916 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5917 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5918 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5919 } },
5920 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5921 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5922 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5923 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5924 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5925 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5926 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5927 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5928 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5929 } },
5930 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5931 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5932 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5933 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5934 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5935 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5936 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5937 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
5938 } },
5939 { },
5940};
5941
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5942enum ioctrl_regs {
5943 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5944 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5945};
5946
5947static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5948 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5949 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5950 { /* sentinel */ },
5951};
5952
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5953static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5954{
5955 int bit = -EINVAL;
5956
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5957 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5958
5959 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5960 bit = pin & 0x1f;
5961
5962 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5963 bit = (pin & 0x1f) + 12;
5964
5965 return bit;
5966}
5967
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5968static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5969 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5970 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5971 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5972 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5973 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5974 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5975 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5976 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5977 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5978 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5979 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5980 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5981 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5982 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5983 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5984 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5985 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5986 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5987 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5988 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5989 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5990 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5991 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5992 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5993 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5994 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5995 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5996 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5997 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5998 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5999 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6000 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6001 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6002 } },
6003 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6004 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6005 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6006 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6007 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6008 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6009 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6010 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6011 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6012 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6013 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6014 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6015 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6016 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6017 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6018 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6019 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6020 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6021 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6022 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6023 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6024 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6025 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6026 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6027 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6028 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6029 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6030 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6031 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6032 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6033 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6034 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6035 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6036 } },
6037 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6038 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6039 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6040 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6041 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6042 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6043 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6044 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6045 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6046 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6047 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
6048 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6049 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6050 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6051 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6052 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6053 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6054 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6055 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6056 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6057 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6058 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6059 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6060 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6061 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6062 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6063 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6064 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6065 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6066 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6067 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6068 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6069 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6070 } },
6071 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6072 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6073 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6074 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6075 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6076 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6077 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6078 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6079 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6080 [ 8] = PIN_NONE,
6081 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6082 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6083 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6084 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6085 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6086 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6087 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6088 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6089 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6090 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6091 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6092 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6093 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6094 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6095 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6096 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6097 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6098 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6099 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6100 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6101 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6102 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6103 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6104 } },
6105 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6106 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6107 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6108 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6109 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6110 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6111 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6112 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6113 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6114 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6115 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6116 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6117 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6118 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6119 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6120 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6121 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6122 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6123 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6124 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6125 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6126 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6127 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6128 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6129 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6130 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6131 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6132 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6133 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6134 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6135 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6136 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6137 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6138 } },
6139 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6140 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6141 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6142 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6143 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6144 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6145 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6146 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6147 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6148 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6149 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6150 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6151 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6152 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6153 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6154 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6155 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6156 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6157 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6158 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6159 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6160 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6161 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6162 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6163 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6164 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6165 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6166 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6167 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6168 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6169 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6170 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6171 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6172 } },
6173 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6174 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6175 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6176 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6177 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6178 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6179 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6180 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6181 [ 7] = PIN_NONE,
6182 [ 8] = PIN_NONE,
6183 [ 9] = PIN_NONE,
6184 [10] = PIN_NONE,
6185 [11] = PIN_NONE,
6186 [12] = PIN_NONE,
6187 [13] = PIN_NONE,
6188 [14] = PIN_NONE,
6189 [15] = PIN_NONE,
6190 [16] = PIN_NONE,
6191 [17] = PIN_NONE,
6192 [18] = PIN_NONE,
6193 [19] = PIN_NONE,
6194 [20] = PIN_NONE,
6195 [21] = PIN_NONE,
6196 [22] = PIN_NONE,
6197 [23] = PIN_NONE,
6198 [24] = PIN_NONE,
6199 [25] = PIN_NONE,
6200 [26] = PIN_NONE,
6201 [27] = PIN_NONE,
6202 [28] = PIN_NONE,
6203 [29] = PIN_NONE,
6204 [30] = PIN_NONE,
6205 [31] = PIN_NONE,
6206 } },
6207 { /* sentinel */ },
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6208};
6209
6210static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6211 unsigned int pin)
6212{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6213 const struct pinmux_bias_reg *reg;
6214 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6215
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6216 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6217 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6218 return PIN_CONFIG_BIAS_DISABLE;
6219
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6220 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6221 return PIN_CONFIG_BIAS_DISABLE;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6222 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6223 return PIN_CONFIG_BIAS_PULL_UP;
6224 else
6225 return PIN_CONFIG_BIAS_PULL_DOWN;
6226}
6227
6228static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6229 unsigned int bias)
6230{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6231 const struct pinmux_bias_reg *reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6232 u32 enable, updown;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6233 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6234
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6235 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6236 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6237 return;
6238
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6239 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6240 if (bias != PIN_CONFIG_BIAS_DISABLE)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6241 enable |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6242
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6243 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6244 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6245 updown |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6246
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6247 sh_pfc_write(pfc, reg->pud, updown);
6248 sh_pfc_write(pfc, reg->puen, enable);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6249}
6250
6251static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6252 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6253 .get_bias = r8a7795_pinmux_get_bias,
6254 .set_bias = r8a7795_pinmux_set_bias,
6255};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6256
6257#ifdef CONFIG_PINCTRL_PFC_R8A774E1
6258const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6259 .name = "r8a774e1_pfc",
6260 .ops = &r8a7795_pinmux_ops,
6261 .unlock_reg = 0xe6060000, /* PMMR */
6262
6263 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6264
6265 .pins = pinmux_pins,
6266 .nr_pins = ARRAY_SIZE(pinmux_pins),
6267 .groups = pinmux_groups.common,
6268 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6269 .functions = pinmux_functions.common,
6270 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6271
6272 .cfg_regs = pinmux_config_regs,
6273 .drive_regs = pinmux_drive_regs,
6274 .bias_regs = pinmux_bias_regs,
6275 .ioctrl_regs = pinmux_ioctrl_regs,
6276
6277 .pinmux_data = pinmux_data,
6278 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6279};
6280#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6281
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6282#ifdef CONFIG_PINCTRL_PFC_R8A7795
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6283const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6284 .name = "r8a77951_pfc",
6285 .ops = &r8a7795_pinmux_ops,
6286 .unlock_reg = 0xe6060000, /* PMMR */
6287
6288 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6289
6290 .pins = pinmux_pins,
6291 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6292 .groups = pinmux_groups.common,
6293 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6294 ARRAY_SIZE(pinmux_groups.automotive),
6295 .functions = pinmux_functions.common,
6296 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6297 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6298
6299 .cfg_regs = pinmux_config_regs,
6300 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6301 .bias_regs = pinmux_bias_regs,
6302 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6303
6304 .pinmux_data = pinmux_data,
6305 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6306};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6307#endif