Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2013 |
| 3 | * Texas Instruments Incorporated. |
| 4 | * Sricharan R <r.sricharan@ti.com> |
| 5 | * |
| 6 | * Derived from OMAP4 done by: |
| 7 | * Aneesh V <aneesh@ti.com> |
| 8 | * |
| 9 | * TI OMAP5 AND DRA7XX common configuration settings |
| 10 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 11 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 12 | * |
| 13 | * For more details, please see the technical documents listed at |
| 14 | * http://www.ti.com/product/omap5432 |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Enric Balletbò i Serra | 2785bb7 | 2013-12-06 21:30:19 +0100 | [diff] [blame] | 17 | #ifndef __CONFIG_TI_OMAP5_COMMON_H |
| 18 | #define __CONFIG_TI_OMAP5_COMMON_H |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 19 | |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 20 | /* Use General purpose timer 1 */ |
| 21 | #define CONFIG_SYS_TIMERBASE GPT2_BASE |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 22 | |
Tom Rini | 2108960 | 2013-08-20 08:53:52 -0400 | [diff] [blame] | 23 | /* |
| 24 | * For the DDR timing information we can either dynamically determine |
| 25 | * the timings to use or use pre-determined timings (based on using the |
| 26 | * dynamic method. Default to the static timing infomation. |
| 27 | */ |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 28 | #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 29 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
| 30 | #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION |
| 31 | #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS |
| 32 | #endif |
| 33 | |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 34 | #define CONFIG_PALMAS_POWER |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 35 | |
| 36 | #include <asm/arch/cpu.h> |
| 37 | #include <asm/arch/omap.h> |
| 38 | |
Nishanth Menon | ad63dd7 | 2015-07-22 18:05:41 -0500 | [diff] [blame] | 39 | #include <configs/ti_armv7_omap.h> |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 40 | |
| 41 | /* |
Tom Rini | b3277f5 | 2013-08-09 11:22:18 -0400 | [diff] [blame] | 42 | * Hardware drivers |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 43 | */ |
Thomas Chou | 52ac443 | 2015-11-19 21:48:12 +0800 | [diff] [blame] | 44 | #define CONFIG_SYS_NS16550_CLK 48000000 |
Lokesh Vutla | 7ee789d | 2017-02-10 20:37:20 +0530 | [diff] [blame] | 45 | #if !defined(CONFIG_DM_SERIAL) |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 46 | #define CONFIG_SYS_NS16550_SERIAL |
| 47 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
Tom Rini | 2accd96 | 2015-09-17 16:47:04 -0400 | [diff] [blame] | 48 | #endif |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 49 | |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 50 | /* |
| 51 | * Environment setup |
| 52 | */ |
Tom Rini | 546c6c1 | 2013-04-05 06:21:45 +0000 | [diff] [blame] | 53 | |
Kishon Vijay Abraham I | 2408076 | 2015-02-23 18:40:20 +0530 | [diff] [blame] | 54 | #ifndef DFUARGS |
| 55 | #define DFUARGS |
| 56 | #endif |
| 57 | |
Semen Protsenko | 334f5bb | 2017-06-14 21:34:23 +0300 | [diff] [blame] | 58 | #include <environment/ti/boot.h> |
Sekhar Nori | 0ea56fe | 2017-04-06 14:52:56 +0530 | [diff] [blame] | 59 | #include <environment/ti/mmc.h> |
| 60 | |
Lokesh Vutla | 6d576a7 | 2014-07-14 19:57:58 +0530 | [diff] [blame] | 61 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 62 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Tom Rini | 96886f2 | 2014-03-28 15:03:29 -0400 | [diff] [blame] | 63 | DEFAULT_LINUX_BOOT_ENV \ |
Lokesh Vutla | b207c47 | 2015-08-28 13:35:07 +0530 | [diff] [blame] | 64 | DEFAULT_MMC_TI_ARGS \ |
Lokesh Vutla | c2913ac | 2016-11-29 11:58:00 +0530 | [diff] [blame] | 65 | DEFAULT_FIT_TI_ARGS \ |
Semen Protsenko | 334f5bb | 2017-06-14 21:34:23 +0300 | [diff] [blame] | 66 | DEFAULT_COMMON_BOOT_TI_ARGS \ |
| 67 | DEFAULT_FDT_TI_ARGS \ |
Kishon Vijay Abraham I | 2408076 | 2015-02-23 18:40:20 +0530 | [diff] [blame] | 68 | DFUARGS \ |
Cooper Jr., Franklin | 07610ab | 2015-04-21 07:51:04 -0500 | [diff] [blame] | 69 | NETARGS \ |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 70 | |
Tom Rini | 2108960 | 2013-08-20 08:53:52 -0400 | [diff] [blame] | 71 | /* |
| 72 | * SPL related defines. The Public RAM memory map the ROM defines the |
Daniel Allred | 36d0824 | 2016-05-19 19:10:50 -0500 | [diff] [blame] | 73 | * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. |
| 74 | * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. |
| 75 | * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and |
Tom Rini | 2108960 | 2013-08-20 08:53:52 -0400 | [diff] [blame] | 76 | * print some information. |
| 77 | */ |
Daniel Allred | 36d0824 | 2016-05-19 19:10:50 -0500 | [diff] [blame] | 78 | #ifdef CONFIG_TI_SECURE_DEVICE |
| 79 | /* |
| 80 | * For memory booting on HS parts, the first 4KB of the internal RAM is |
| 81 | * reserved for secure world use and the flash loader image is |
| 82 | * preceded by a secure certificate. The SPL will therefore run in internal |
| 83 | * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). |
| 84 | */ |
| 85 | #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 |
| 86 | #define CONFIG_SPL_TEXT_BASE 0x40301350 |
Daniel Allred | 420ffad | 2016-09-02 00:40:23 -0500 | [diff] [blame] | 87 | /* If no specific start address is specified then the secure EMIF |
| 88 | * region will be placed at the end of the DDR space. In order to prevent |
| 89 | * the main u-boot relocation from clobbering that memory and causing a |
| 90 | * firewall violation, we tell u-boot that memory is protected RAM (PRAM) |
| 91 | */ |
| 92 | #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) |
| 93 | #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 |
| 94 | #endif |
Daniel Allred | 36d0824 | 2016-05-19 19:10:50 -0500 | [diff] [blame] | 95 | #else |
| 96 | /* |
| 97 | * For all booting on GP parts, the flash loader image is |
| 98 | * downloaded into internal RAM at address 0x40300000. |
| 99 | */ |
| 100 | #define CONFIG_SPL_TEXT_BASE 0x40300000 |
| 101 | #endif |
| 102 | |
Tom Rini | d9f808d | 2014-04-03 07:52:53 -0400 | [diff] [blame] | 103 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 104 | (128 << 20)) |
Lokesh Vutla | 3e716e2 | 2013-02-17 23:34:35 +0000 | [diff] [blame] | 105 | |
Enric Balletbò i Serra | 4785859 | 2013-12-06 21:30:20 +0100 | [diff] [blame] | 106 | #ifdef CONFIG_NAND |
| 107 | #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ |
| 108 | #endif |
| 109 | |
Mugunthan V N | d032015 | 2015-09-29 14:42:26 +0530 | [diff] [blame] | 110 | #ifdef CONFIG_SPL_BUILD |
Mugunthan V N | 6987f2d | 2015-12-24 16:08:18 +0530 | [diff] [blame] | 111 | #undef CONFIG_TIMER |
Mugunthan V N | d032015 | 2015-09-29 14:42:26 +0530 | [diff] [blame] | 112 | #endif |
| 113 | |
Enric Balletbò i Serra | 2785bb7 | 2013-12-06 21:30:19 +0100 | [diff] [blame] | 114 | #endif /* __CONFIG_TI_OMAP5_COMMON_H */ |