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Lokesh Vutla3e716e22013-02-17 23:34:35 +00001/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated.
4 * Sricharan R <r.sricharan@ti.com>
5 *
6 * Derived from OMAP4 done by:
7 * Aneesh V <aneesh@ti.com>
8 *
9 * TI OMAP5 AND DRA7XX common configuration settings
10 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Tom Rinib3277f52013-08-09 11:22:18 -040012 *
13 * For more details, please see the technical documents listed at
14 * http://www.ti.com/product/omap5432
Lokesh Vutla3e716e22013-02-17 23:34:35 +000015 */
16
Enric Balletbò i Serra2785bb72013-12-06 21:30:19 +010017#ifndef __CONFIG_TI_OMAP5_COMMON_H
18#define __CONFIG_TI_OMAP5_COMMON_H
Lokesh Vutla3e716e22013-02-17 23:34:35 +000019
Tom Rinib3277f52013-08-09 11:22:18 -040020/* Use General purpose timer 1 */
21#define CONFIG_SYS_TIMERBASE GPT2_BASE
Lokesh Vutla3e716e22013-02-17 23:34:35 +000022
Tom Rini21089602013-08-20 08:53:52 -040023/*
24 * For the DDR timing information we can either dynamically determine
25 * the timings to use or use pre-determined timings (based on using the
26 * dynamic method. Default to the static timing infomation.
27 */
Tom Rinib3277f52013-08-09 11:22:18 -040028#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
Tom Rinib3277f52013-08-09 11:22:18 -040029#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
30#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
31#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
32#endif
33
Tom Rinib3277f52013-08-09 11:22:18 -040034#define CONFIG_PALMAS_POWER
Tom Rinib3277f52013-08-09 11:22:18 -040035
36#include <asm/arch/cpu.h>
37#include <asm/arch/omap.h>
38
Nishanth Menonad63dd72015-07-22 18:05:41 -050039#include <configs/ti_armv7_omap.h>
Lokesh Vutla3e716e22013-02-17 23:34:35 +000040
41/*
Tom Rinib3277f52013-08-09 11:22:18 -040042 * Hardware drivers
Lokesh Vutla3e716e22013-02-17 23:34:35 +000043 */
Thomas Chou52ac4432015-11-19 21:48:12 +080044#define CONFIG_SYS_NS16550_CLK 48000000
Lokesh Vutla7ee789d2017-02-10 20:37:20 +053045#if !defined(CONFIG_DM_SERIAL)
Lokesh Vutla3e716e22013-02-17 23:34:35 +000046#define CONFIG_SYS_NS16550_SERIAL
47#define CONFIG_SYS_NS16550_REG_SIZE (-4)
Tom Rini2accd962015-09-17 16:47:04 -040048#endif
Lokesh Vutla3e716e22013-02-17 23:34:35 +000049
Lokesh Vutla3e716e22013-02-17 23:34:35 +000050/*
51 * Environment setup
52 */
Tom Rini546c6c12013-04-05 06:21:45 +000053
Kishon Vijay Abraham I24080762015-02-23 18:40:20 +053054#ifndef DFUARGS
55#define DFUARGS
56#endif
57
Semen Protsenko334f5bb2017-06-14 21:34:23 +030058#include <environment/ti/boot.h>
Sekhar Nori0ea56fe2017-04-06 14:52:56 +053059#include <environment/ti/mmc.h>
60
Lokesh Vutla6d576a72014-07-14 19:57:58 +053061#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Lokesh Vutla3e716e22013-02-17 23:34:35 +000062#define CONFIG_EXTRA_ENV_SETTINGS \
Tom Rini96886f22014-03-28 15:03:29 -040063 DEFAULT_LINUX_BOOT_ENV \
Lokesh Vutlab207c472015-08-28 13:35:07 +053064 DEFAULT_MMC_TI_ARGS \
Lokesh Vutlac2913ac2016-11-29 11:58:00 +053065 DEFAULT_FIT_TI_ARGS \
Semen Protsenko334f5bb2017-06-14 21:34:23 +030066 DEFAULT_COMMON_BOOT_TI_ARGS \
67 DEFAULT_FDT_TI_ARGS \
Kishon Vijay Abraham I24080762015-02-23 18:40:20 +053068 DFUARGS \
Cooper Jr., Franklin07610ab2015-04-21 07:51:04 -050069 NETARGS \
Lokesh Vutla3e716e22013-02-17 23:34:35 +000070
Tom Rini21089602013-08-20 08:53:52 -040071/*
72 * SPL related defines. The Public RAM memory map the ROM defines the
Daniel Allred36d08242016-05-19 19:10:50 -050073 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
74 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
75 * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
Tom Rini21089602013-08-20 08:53:52 -040076 * print some information.
77 */
Daniel Allred36d08242016-05-19 19:10:50 -050078#ifdef CONFIG_TI_SECURE_DEVICE
79/*
80 * For memory booting on HS parts, the first 4KB of the internal RAM is
81 * reserved for secure world use and the flash loader image is
82 * preceded by a secure certificate. The SPL will therefore run in internal
83 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
84 */
85#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
86#define CONFIG_SPL_TEXT_BASE 0x40301350
Daniel Allred420ffad2016-09-02 00:40:23 -050087/* If no specific start address is specified then the secure EMIF
88 * region will be placed at the end of the DDR space. In order to prevent
89 * the main u-boot relocation from clobbering that memory and causing a
90 * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
91 */
92#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
93#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
94#endif
Daniel Allred36d08242016-05-19 19:10:50 -050095#else
96/*
97 * For all booting on GP parts, the flash loader image is
98 * downloaded into internal RAM at address 0x40300000.
99 */
100#define CONFIG_SPL_TEXT_BASE 0x40300000
101#endif
102
Tom Rinid9f808d2014-04-03 07:52:53 -0400103#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
104 (128 << 20))
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000105
Enric Balletbò i Serra47858592013-12-06 21:30:20 +0100106#ifdef CONFIG_NAND
107#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
108#endif
109
Mugunthan V Nd0320152015-09-29 14:42:26 +0530110#ifdef CONFIG_SPL_BUILD
Mugunthan V N6987f2d2015-12-24 16:08:18 +0530111#undef CONFIG_TIMER
Mugunthan V Nd0320152015-09-29 14:42:26 +0530112#endif
113
Enric Balletbò i Serra2785bb72013-12-06 21:30:19 +0100114#endif /* __CONFIG_TI_OMAP5_COMMON_H */