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Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03001/*
2 * include/configs/silk.h
3 * This file is silk board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __SILK_H
12#define __SILK_H
13
14#undef DEBUG
15#define CONFIG_R8A7794
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090016#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk"
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030017
18#include "rcar-gen2-common.h"
19
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090020#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030021#define CONFIG_SYS_TEXT_BASE 0x70000000
22#else
23#define CONFIG_SYS_TEXT_BASE 0xE6304000
24#endif
25
Nobuhiro Iwamatsu7c112732015-10-10 05:58:28 +090026#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030027#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28#else
29#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
30#endif
31#define STACK_AREA_SIZE 0xC000
32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
36#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
39
40/* SCIF */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030041
42/* FLASH */
43#define CONFIG_SPI
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030044#define CONFIG_SH_QSPI
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030045#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030046
47/* SH Ether */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030048#define CONFIG_SH_ETHER
49#define CONFIG_SH_ETHER_USE_PORT 0
50#define CONFIG_SH_ETHER_PHY_ADDR 0x1
51#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
52#define CONFIG_SH_ETHER_CACHE_WRITEBACK
53#define CONFIG_SH_ETHER_CACHE_INVALIDATE
54#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030055#define CONFIG_BITBANGMII
56#define CONFIG_BITBANGMII_MULTI
57
58/* Board Clock */
59#define RMOBILE_XTAL_CLK 20000000u
60#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
61#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
62#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
63#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030064
65#define CONFIG_SYS_TMU_CLK_DIV 4
66
67/* i2c */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030068#define CONFIG_SYS_I2C
69#define CONFIG_SYS_I2C_SH
70#define CONFIG_SYS_I2C_SLAVE 0x7F
71#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
72#define CONFIG_SYS_I2C_SH_SPEED0 400000
73#define CONFIG_SYS_I2C_SH_SPEED1 400000
74#define CONFIG_SYS_I2C_SH_SPEED2 400000
75#define CONFIG_SH_I2C_DATA_HIGH 4
76#define CONFIG_SH_I2C_DATA_LOW 5
77#define CONFIG_SH_I2C_CLOCK 10000000
78
79#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
80
81/* USB */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030082#define CONFIG_USB_EHCI_RMOBILE
83#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
84
85/* MMCIF */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030086#define CONFIG_SH_MMCIF
87#define CONFIG_SH_MMCIF_ADDR 0xee200000
88#define CONFIG_SH_MMCIF_CLK 48000000
89
Vladimir Barinovc5951332015-02-24 18:55:46 +020090/* SDHI */
91#define CONFIG_SH_SDHI_FREQ 97500000
92
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030093/* Module stop status bits */
94/* INTC-RT */
95#define CONFIG_SMSTP0_ENA 0x00400000
96/* MSIF */
97#define CONFIG_SMSTP2_ENA 0x00002000
98/* INTC-SYS, IRQC */
99#define CONFIG_SMSTP4_ENA 0x00000180
100/* SCIF2 */
101#define CONFIG_SMSTP7_ENA 0x00080000
102
103#endif /* __SILK_H */