blob: 4387082b263e7fb12c86f122347e821b5554dfbd [file] [log] [blame]
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -07001/**
2 * (C) Copyright 2014, Cavium Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5**/
6
7#ifndef __THUNDERX_88XX_H__
8#define __THUNDERX_88XX_H__
9
10#define CONFIG_REMAKE_ELF
11
12#define CONFIG_THUNDERX
13
14#define CONFIG_SYS_64BIT
15
16#define CONFIG_SYS_NO_FLASH
17
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070018#define MEM_BASE 0x00500000
19
Sergey Temerkhanov62dce242015-10-14 09:55:51 -070020#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
21
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070022/* Link Definitions */
23#define CONFIG_SYS_TEXT_BASE 0x00500000
24#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
25
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070026/* SMP Spin Table Definitions */
27#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
28
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070029/* Generic Timer Definitions */
30#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
31
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070032#define CONFIG_SYS_MEMTEST_START MEM_BASE
33#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
34
35/* Size of malloc() pool */
36#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
37
38/* PL011 Serial Configuration */
39
40#define CONFIG_PL01X_SERIAL
41#define CONFIG_PL011_CLOCK 24000000
42#define CONFIG_CONS_INDEX 1
43
44/* Generic Interrupt Controller Definitions */
45#define GICD_BASE (0x801000000000)
46#define GICR_BASE (0x801000002000)
47#define CONFIG_SYS_SERIAL0 0x87e024000000
48#define CONFIG_SYS_SERIAL1 0x87e025000000
49
50#define CONFIG_BAUDRATE 115200
51
52/* Command line configuration */
53#define CONFIG_MENU
54
55/* BOOTP options */
56#define CONFIG_BOOTP_BOOTFILESIZE
57#define CONFIG_BOOTP_BOOTPATH
58#define CONFIG_BOOTP_GATEWAY
59#define CONFIG_BOOTP_HOSTNAME
60#define CONFIG_BOOTP_PXE
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070061
62/* Miscellaneous configurable options */
63#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
64
65/* Physical Memory Map */
66#define CONFIG_NR_DRAM_BANKS 1
67#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
68#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
69#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
70
71/* Initial environment variables */
72#define UBOOT_IMG_HEAD_SIZE 0x40
73/* C80000 - 0x40 */
74#define CONFIG_EXTRA_ENV_SETTINGS \
75 "kernel_addr=08007ffc0\0" \
76 "fdt_addr=0x94C00000\0" \
77 "fdt_high=0x9fffffff\0"
78
79#define CONFIG_BOOTARGS \
80 "console=ttyAMA0,115200n8 " \
81 "earlycon=pl011,0x87e024000000 " \
82 "debug maxcpus=48 rootwait rw "\
83 "root=/dev/sda2 coherent_pool=16M"
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070084
85/* Do not preserve environment */
86#define CONFIG_ENV_IS_NOWHERE 1
87#define CONFIG_ENV_SIZE 0x1000
88
89/* Monitor Command Prompt */
90#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
91#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
92 sizeof(CONFIG_SYS_PROMPT) + 16)
Sergey Temerkhanov69f7a032015-10-14 09:55:50 -070093#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
94#define CONFIG_SYS_LONGHELP
95#define CONFIG_CMDLINE_EDITING 1
96#define CONFIG_SYS_MAXARGS 64 /* max command args */
97#define CONFIG_NO_RELOCATION 1
98#define CONFIG_LIB_RAND
99#define PLL_REF_CLK 50000000 /* 50 MHz */
100#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
101
102#endif /* __THUNDERX_88XX_H__ */