Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000-2004 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 85d6531 | 2019-12-28 10:44:58 -0700 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 9 | #include <mpc8xx.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 11 | #include <asm/processor.h> |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 12 | #include <asm/io.h> |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 13 | |
| 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 16 | /* |
| 17 | * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ |
| 18 | */ |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 19 | int get_clocks(void) |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 20 | { |
Christophe Leroy | 5c59bdf | 2018-03-16 17:20:33 +0100 | [diff] [blame] | 21 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
Christophe Leroy | 394f9b3 | 2017-07-06 10:33:13 +0200 | [diff] [blame] | 22 | uint sccr = in_be32(&immap->im_clkrst.car_sccr); |
Christophe Leroy | 297cbac | 2017-07-13 15:09:44 +0200 | [diff] [blame] | 23 | uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); |
| 24 | |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 25 | /* |
| 26 | * If for some reason measuring the gclk frequency won't |
| 27 | * work, we return the hardwired value. |
| 28 | * (For example, the cogent CMA286-60 CPU module has no |
| 29 | * separate oscillator for PITRTCLK) |
| 30 | */ |
| 31 | gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; |
| 32 | |
| 33 | if ((sccr & SCCR_EBDF11) == 0) { |
| 34 | /* No Bus Divider active */ |
| 35 | gd->bus_clk = gd->cpu_clk; |
| 36 | } else { |
| 37 | /* The MPC8xx has only one BDF: half clock speed */ |
| 38 | gd->bus_clk = gd->cpu_clk / 2; |
| 39 | } |
| 40 | |
Christophe Leroy | 297cbac | 2017-07-13 15:09:44 +0200 | [diff] [blame] | 41 | gd->arch.brg_clk = gd->cpu_clk / divider; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 42 | |
Christophe Leroy | 48f896d | 2017-07-06 10:33:17 +0200 | [diff] [blame] | 43 | return 0; |
Christophe Leroy | 069fa83 | 2017-07-06 10:23:22 +0200 | [diff] [blame] | 44 | } |