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git01.mediatek.com / filogic / uboot / d16872537f7dfefa075b35c02bc82ab010cb338c / . / arch / arm / dts / r8a779g0-u-boot.dtsi
blob: 90f021299c592ef2710d6a4ce066993e43ca2a93 [file] [log] [blame]
Hai Pham050b3b42023-02-28 22:37:05 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source extras for U-Boot on R-Car R8A779G0 SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include "r8a779x-u-boot.dtsi"
9
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame^]10/ {
11 binman: binman {
12 multiple-images;
13
14 section {
15 filename = "flash.bin";
16 pad-byte = <0xff>;
17
18 /* Offset 0x0000 set to 0x0000_0000 */
19 fill@0 {
20 offset = <0x0>;
21 size = <0x4>;
22 fill-byte = [00];
23 };
24
25 /* Offset 0x300c set to 0x0000_0000 */
26 fill@300c {
27 offset = <0x300c>;
28 size = <0x4>;
29 fill-byte = [00];
30 };
31
32 /* Offset 0x3154 set to 0xeb21_0000 */
33 fill@3154 {
34 offset = <0x3154>;
35 size = <0x2>;
36 fill-byte = [00];
37 };
38
39 fill@3156 {
40 offset = <0x3156>;
41 size = <0x1>;
42 fill-byte = [21];
43 };
44
45 fill@3157 {
46 offset = <0x3157>;
47 size = <0x1>;
48 fill-byte = [eb];
49 };
50
51 /* Offset 0x3264 set to 0x0003_b000 */
52 fill@3264 {
53 offset = <0x3264>;
54 size = <0x1>;
55 fill-byte = [00];
56 };
57
58 fill@3265 {
59 offset = <0x3265>;
60 size = <0x1>;
61 fill-byte = [b0];
62 };
63
64 fill@3266 {
65 offset = <0x3266>;
66 size = <0x1>;
67 fill-byte = [03];
68 };
69
70 fill@3267 {
71 offset = <0x3267>;
72 size = <0x1>;
73 fill-byte = [00];
74 };
75
76 u-boot-spl {
77 offset = <0x40000>;
78 align-end = <4>;
79 };
80
81 u-boot {
82 offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
83 filename = "u-boot.itb";
84
85 fit {
86 description = "U-Boot mainline";
87 fit,fdt-list = "of-list";
88 #address-cells = <1>;
89
90 images {
91 uboot {
92 arch = "arm64";
93 compression = "none";
94 description = "U-Boot (64-bit)";
95 type = "standalone";
96 /*
97 * This is in DRAM. We cannot
98 * use TEXT_BASE here because
99 * this system uses PIE build
100 * and TEXT_BASE=0x0 .
101 */
102 entry = <0x44100000>;
103 load = <0x44100000>;
104
105 uboot-blob {
106 filename = "u-boot-nodtb.bin";
107 type = "blob-ext";
108 };
109 };
110
111 @fdt-SEQ {
112 compression = "none";
113 description = "NAME";
114 type = "flat_dt";
115
116 uboot-fdt-blob {
117 filename = "u-boot.dtb";
118 type = "blob-ext";
119 };
120 };
121 };
122
123 configurations {
124 default = "@config-DEFAULT-SEQ";
125
126 @config-SEQ {
127 description = "NAME";
128 fdt = "fdt-SEQ";
129 firmware = "uboot";
130 };
131 };
132 };
133 };
134 };
135 };
136};
137
138&cpg {
139 bootph-all;
140};
141
142&extalr_clk {
143 bootph-all;
144};
145
146&hscif0 {
147 bootph-all;
148};
149
150&hscif0_pins {
151 bootph-all;
152};
153
154&pfc {
155 bootph-all;
156};
157
Marek Vasut69bdcf62023-06-20 00:41:49 +0200[diff] [blame]158&rpc {
Marek Vasut69bdcf62023-06-20 00:41:49 +0200[diff] [blame]159 bank-width = <2>;
160 num-cs = <1>;
Hai Pham050b3b42023-02-28 22:37:05 +0100[diff] [blame]161};
162
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame^]163&rst {
Hai Pham050b3b42023-02-28 22:37:05 +0100[diff] [blame]164 bootph-all;
165};
Marek Vasutd07e3722024-12-12 14:34:31 +0100[diff] [blame]166
167&soc {
168 ram@e6780000 { /* DBSC5 */
169 compatible = "renesas,r8a779g0-dbsc";
170 reg = <0 0xe6780000 0 0x80000>;
171 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
172 status = "okay";
173 bootph-all;
174 };
175
176 ram@ffec0000 { /* RT-VRAM */
177 compatible = "renesas,r8a779g0-rtvram";
178 reg = <0 0xffec0000 0 0xf000>;
179 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
180 status = "okay";
181 bootph-all;
182 };
183};