| Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2019 - All Rights Reserved |
| 4 | * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. |
| 5 | */ |
| 6 | |
| 7 | #include "stm32mp151.dtsi" |
| 8 | |
| 9 | / { |
| 10 | cpus { |
| 11 | cpu1: cpu@1 { |
| 12 | compatible = "arm,cortex-a7"; |
| 13 | device_type = "cpu"; |
| 14 | reg = <1>; |
| 15 | }; |
| 16 | }; |
| 17 | |
| 18 | soc { |
| 19 | m_can1: can@4400e000 { |
| 20 | compatible = "bosch,m_can"; |
| 21 | reg = <0x4400e000 0x400>, <0x44011000 0x1400>; |
| 22 | reg-names = "m_can", "message_ram"; |
| 23 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| 24 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 25 | interrupt-names = "int0", "int1"; |
| 26 | clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; |
| 27 | clock-names = "hclk", "cclk"; |
| 28 | bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; |
| 29 | status = "disabled"; |
| 30 | }; |
| 31 | |
| 32 | m_can2: can@4400f000 { |
| 33 | compatible = "bosch,m_can"; |
| 34 | reg = <0x4400f000 0x400>, <0x44011000 0x2800>; |
| 35 | reg-names = "m_can", "message_ram"; |
| 36 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
| 37 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 38 | interrupt-names = "int0", "int1"; |
| 39 | clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; |
| 40 | clock-names = "hclk", "cclk"; |
| 41 | bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; |
| 42 | status = "disabled"; |
| 43 | }; |
| 44 | }; |
| 45 | }; |