| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | #include <s3c2410.h> |
| 30 | |
| 31 | /* ------------------------------------------------------------------------- */ |
| 32 | |
| 33 | #define FCLK_SPEED 1 |
| 34 | |
| 35 | #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ |
| 36 | #define M_MDIV 0xC3 |
| 37 | #define M_PDIV 0x4 |
| 38 | #define M_SDIV 0x1 |
| 39 | #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ |
| 40 | #define M_MDIV 0xA1 |
| 41 | #define M_PDIV 0x3 |
| 42 | #define M_SDIV 0x1 |
| 43 | #endif |
| 44 | |
| 45 | #define USB_CLOCK 1 |
| 46 | |
| 47 | #if USB_CLOCK==0 |
| 48 | #define U_M_MDIV 0xA1 |
| 49 | #define U_M_PDIV 0x3 |
| 50 | #define U_M_SDIV 0x1 |
| 51 | #elif USB_CLOCK==1 |
| 52 | #define U_M_MDIV 0x48 |
| 53 | #define U_M_PDIV 0x3 |
| 54 | #define U_M_SDIV 0x2 |
| 55 | #endif |
| 56 | |
| 57 | static inline void delay (unsigned long loops) |
| 58 | { |
| 59 | __asm__ volatile ("1:\n" |
| 60 | "subs %0, %1, #1\n" |
| 61 | "bne 1b":"=r" (loops):"0" (loops)); |
| 62 | } |
| 63 | |
| 64 | /* |
| 65 | * Miscellaneous platform dependent initialisations |
| 66 | */ |
| 67 | |
| 68 | int board_init (void) |
| 69 | { |
| 70 | DECLARE_GLOBAL_DATA_PTR; |
| 71 | |
| 72 | /* to reduce PLL lock time, adjust the LOCKTIME register */ |
| 73 | rLOCKTIME = 0xFFFFFF; |
| 74 | |
| 75 | /* configure MPLL */ |
| 76 | rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); |
| 77 | |
| 78 | /* some delay between MPLL and UPLL */ |
| 79 | delay (4000); |
| 80 | |
| 81 | /* configure UPLL */ |
| 82 | rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); |
| 83 | |
| 84 | /* some delay between MPLL and UPLL */ |
| 85 | delay (8000); |
| 86 | |
| 87 | /* set up the I/O ports */ |
| 88 | rGPACON = 0x007FFFFF; |
| 89 | rGPBCON = 0x00044555; |
| 90 | rGPBUP = 0x000007FF; |
| 91 | rGPCCON = 0xAAAAAAAA; |
| 92 | rGPCUP = 0x0000FFFF; |
| 93 | rGPDCON = 0xAAAAAAAA; |
| 94 | rGPDUP = 0x0000FFFF; |
| 95 | rGPECON = 0xAAAAAAAA; |
| 96 | rGPEUP = 0x0000FFFF; |
| 97 | rGPFCON = 0x000055AA; |
| 98 | rGPFUP = 0x000000FF; |
| 99 | rGPGCON = 0xFF95FFBA; |
| 100 | rGPGUP = 0x0000FFFF; |
| 101 | rGPHCON = 0x002AFAAA; |
| 102 | rGPHUP = 0x000007FF; |
| 103 | |
| 104 | /* arch number of SMDK2410-Board */ |
| 105 | gd->bd->bi_arch_number = 193; |
| 106 | |
| 107 | /* adress of boot parameters */ |
| 108 | gd->bd->bi_boot_params = 0x30000100; |
| 109 | |
| 110 | icache_enable(); |
| 111 | dcache_enable(); |
| 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | int dram_init (void) |
| 117 | { |
| 118 | DECLARE_GLOBAL_DATA_PTR; |
| 119 | |
| 120 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 121 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 122 | |
| 123 | return 0; |
| 124 | } |