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Daniel Hellstrome045a4c2008-03-26 23:34:47 +01001/* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
4 * EP2S60.
5 *
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * (C) Copyright 2008
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
11 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010013 */
14
15#ifndef __CONFIG_H__
16#define __CONFIG_H__
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010023/* Altera NIOS Development board, Stratix II board */
Wolfgang Denka1be4762008-05-20 16:00:29 +020024#define CONFIG_GR_EP2S60 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010025
26/* CPU / AMBA BUS configuration */
Wolfgang Denka1be4762008-05-20 16:00:29 +020027#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010028
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010029/* Define this is the GR-2S60-MEZZ mezzanine is available and you
30 * want to use the USB and GRETH functionality of the board
31 */
32#undef GR_2S60_MEZZ
33
34#ifdef GR_2S60_MEZZ
35#define USE_GRETH 1
36#define USE_GRUSB 1
37#endif
38
39/*
40 * Serial console configuration
41 */
42#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010044
45/* Partitions */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010046
47/*
48 * Supported commands
49 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010050#define CONFIG_CMD_REGINFO
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010051#define CONFIG_CMD_DIAG
52#define CONFIG_CMD_IRQ
53
54/* USB support */
55#if USE_GRUSB
56#define CONFIG_USB_UHCI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010057/* Enable needed helper functions */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010058#endif
59
60/*
61 * Autobooting
62 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010063
64#define CONFIG_PREBOOT "echo;" \
65 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
66 "echo"
67
68#undef CONFIG_BOOTARGS
69
70#define CONFIG_EXTRA_ENV_SETTINGS \
71 "netdev=eth0\0" \
72 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
73 "nfsroot=${serverip}:${rootpath}\0" \
74 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
75 "addip=setenv bootargs ${bootargs} " \
76 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
77 ":${hostname}:${netdev}:off panic=1\0" \
78 "flash_nfs=run nfsargs addip;" \
79 "bootm ${kernel_addr}\0" \
80 "flash_self=run ramargs addip;" \
81 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
82 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
83 "scratch=40800000\0" \
Mike Frysingerc3c6bf12011-10-12 19:47:51 +000084 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010085 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
86 ""
87
88#define CONFIG_NETMASK 255.255.255.0
89#define CONFIG_GATEWAYIP 192.168.0.1
90#define CONFIG_SERVERIP 192.168.0.20
91#define CONFIG_IPADDR 192.168.0.207
Joe Hershberger257ff782011-10-13 13:03:47 +000092#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010093#define CONFIG_HOSTNAME ml401
Joe Hershbergere4da2482011-10-13 13:03:48 +000094#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010095
96#define CONFIG_BOOTCOMMAND "run flash_self"
97
98/* Memory MAP
99 *
100 * Flash:
101 * |--------------------------------|
102 * | 0x00000000 Text & Data & BSS | *
103 * | for Monitor | *
104 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
105 * | UNUSED / Growth | * 256kb
106 * |--------------------------------|
107 * | 0x00050000 Base custom area | *
108 * | kernel / FS | *
109 * | | * Rest of Flash
110 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
111 * | END-0x00008000 Environment | * 32kb
112 * |--------------------------------|
113 *
114 *
115 *
116 * Main Memory:
117 * |--------------------------------|
118 * | UNUSED / scratch area |
119 * | |
120 * | |
121 * | |
122 * | |
123 * |--------------------------------|
124 * | Monitor .Text / .DATA / .BSS | * 512kb
125 * | Relocated! | *
126 * |--------------------------------|
127 * | Monitor Malloc | * 128kb (contains relocated environment)
128 * |--------------------------------|
129 * | Monitor/kernel STACK | * 64kb
130 * |--------------------------------|
131 * | Page Table for MMU systems | * 2k
132 * |--------------------------------|
133 * | PROM Code accessed from Linux | * 6kb-128b
134 * |--------------------------------|
135 * | Global data (avail from kernel)| * 128b
136 * |--------------------------------|
137 *
138 */
139
140/*
141 * Flash configuration (8,16 or 32 MB)
142 * TEXT base always at 0xFFF00000
143 * ENV_ADDR always at 0xFFF40000
144 * FLASH_BASE at 0xFC000000 for 64 MB
145 * 0xFE000000 for 32 MB
146 * 0xFF000000 for 16 MB
147 * 0xFF800000 for 8 MB
148 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_BASE 0x00000000
150#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100151
152#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
154#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100155
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
157#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
158#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
159#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
160#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100161
162/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200164#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_CFI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100166/* Bypass cache when reading regs from flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100168/* Buffered writes (32byte/go) instead of single accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100170
171/*
172 * Environment settings
173 */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200174/*#define CONFIG_ENV_IS_NOWHERE 1*/
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200175#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200176/* CONFIG_ENV_ADDR need to be at sector boundary */
177#define CONFIG_ENV_SIZE 0x8000
178#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100180#define CONFIG_ENV_OVERWRITE 1
181
182/*
183 * Memory map
184 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_SDRAM_BASE 0x40000000
186#define CONFIG_SYS_SDRAM_SIZE 0x02000000
187#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100188
189/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#undef CONFIG_SYS_SRAM_BASE
191#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
194#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
195#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100196
Wolfgang Denk0191e472010-10-26 14:34:52 +0200197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100198
Wolfgang Denk0191e472010-10-26 14:34:52 +0200199#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100201
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
203#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100204
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
207# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100208#endif
209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
211#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
215#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100216
217/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
219#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100220
221/* make un relocated address from relocated address */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200222#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100223
224/*
225 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
226 * with a PHY is attached the GRETH can be used on this board.
227 * Define USE_GRETH in order to use the mezzanine provided PHY with the
228 * onchip GRETH network MAC, note that this is not supported by the
229 * template design.
230 */
231#ifndef USE_GRETH
232
233/* USE SMC91C111 MAC */
Ben Warren0fd6aae2009-10-04 22:37:03 -0700234#define CONFIG_SMC91111 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100235#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
236#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
237#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
238/*#define CONFIG_SHOW_ACTIVITY*/
239#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
240
241#else
242
243/* USE GRETH Ethernet Driver */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100244#define CONFIG_GRETH 1
Masahiro Yamadacbafcdf2015-05-26 10:58:31 +0900245#endif
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100246
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100247#define CONFIG_PHY_ADDR 0x00
248
249/*
250 * Miscellaneous configurable options
251 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_LONGHELP /* undef to save memory */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100253#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200254#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100255#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100257#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
259#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
260#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100261
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
263#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100264
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100266
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100267/*-----------------------------------------------------------------------
268 * USB stuff
269 *-----------------------------------------------------------------------
270 */
271#define CONFIG_USB_CLOCK 0x0001BBBB
272#define CONFIG_USB_CONFIG 0x00005000
273
274/***** Gaisler GRLIB IP-Cores Config ********/
275
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_GRLIB_SDRAM 0
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100277
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100278/* No SDRAM Configuration */
279#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
280
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100281/* See, GRLIB Docs (grip.pdf) on how to set up
282 * These the memory controller registers.
283 */
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100284#define CONFIG_SYS_GRLIB_ESA_MCTRL1
285#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
286#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
287#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100288
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100289/* GRLIB FT-MCTRL configuration */
290#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
291#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
292#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
293#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100294
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100295/* DDR controller */
296#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
297#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100298
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100299/* no DDR2 Controller */
300#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100301
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100302/* default kernel command line */
303#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
304
305#endif /* __CONFIG_H */