Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2005-2006 Atmel Corporation |
| 3 | * |
| 4 | * Configuration settings for the ATSTK1002 CPU daughterboard |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 7 | */ |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
Andreas Bießmann | 94156fa | 2010-11-04 23:15:30 +0000 | [diff] [blame] | 11 | #include <asm/arch/hardware.h> |
Haavard Skinnemoen | 23f62f1 | 2008-05-19 11:36:28 +0200 | [diff] [blame] | 12 | |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 13 | #define CONFIG_AT32AP |
| 14 | #define CONFIG_AT32AP7000 |
| 15 | #define CONFIG_ATSTK1002 |
| 16 | #define CONFIG_ATSTK1000 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 17 | |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 18 | /* |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 19 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL |
| 20 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the |
| 21 | * PLL frequency. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 23 | */ |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 24 | #define CONFIG_PLL |
| 25 | #define CONFIG_SYS_POWER_MANAGER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_OSC0_HZ 20000000 |
| 27 | #define CONFIG_SYS_PLL0_DIV 1 |
| 28 | #define CONFIG_SYS_PLL0_MUL 7 |
| 29 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 30 | /* |
| 31 | * Set the CPU running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 33 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 34 | #define CONFIG_SYS_CLKDIV_CPU 0 |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 35 | /* |
| 36 | * Set the HSB running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 37 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 38 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | #define CONFIG_SYS_CLKDIV_HSB 1 |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 40 | /* |
| 41 | * Set the PBA running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 43 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | #define CONFIG_SYS_CLKDIV_PBA 2 |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 45 | /* |
| 46 | * Set the PBB running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
Eirik Aanonsen | 9677534 | 2007-09-12 13:32:37 +0200 | [diff] [blame] | 48 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_CLKDIV_PBB 1 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 50 | |
Haavard Skinnemoen | c6f292f | 2010-08-12 13:52:54 +0700 | [diff] [blame] | 51 | /* Reserve VM regions for SDRAM and NOR flash */ |
| 52 | #define CONFIG_SYS_NR_VM_REGIONS 2 |
| 53 | |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 54 | /* |
| 55 | * The PLLOPT register controls the PLL like this: |
| 56 | * icp = PLLOPT<2> |
| 57 | * ivco = PLLOPT<1:0> |
| 58 | * |
| 59 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). |
| 60 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_PLL0_OPT 0x04 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 62 | |
Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 63 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 |
| 64 | #define CONFIG_USART_ID 1 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 65 | |
| 66 | /* User serviceable stuff */ |
Haavard Skinnemoen | e034f52 | 2006-12-17 18:56:46 +0100 | [diff] [blame] | 67 | |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 68 | #define CONFIG_CMDLINE_TAG |
| 69 | #define CONFIG_SETUP_MEMORY_TAGS |
| 70 | #define CONFIG_INITRD_TAG |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 71 | |
| 72 | #define CONFIG_STACKSIZE (2048) |
| 73 | |
| 74 | #define CONFIG_BAUDRATE 115200 |
| 75 | #define CONFIG_BOOTARGS \ |
Eirik Aanonsen | b4ba6c6 | 2007-09-18 08:47:20 +0200 | [diff] [blame] | 76 | "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" |
Haavard Skinnemoen | 1ec8427 | 2007-03-21 19:47:36 +0100 | [diff] [blame] | 77 | |
| 78 | #define CONFIG_BOOTCOMMAND \ |
| 79 | "fsload; bootm $(fileaddr)" |
| 80 | |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 81 | |
Haavard Skinnemoen | 58f4c26 | 2006-12-17 17:14:30 +0100 | [diff] [blame] | 82 | /* |
Haavard Skinnemoen | b4d8502 | 2007-10-24 15:48:37 +0200 | [diff] [blame] | 83 | * After booting the board for the first time, new ethernet addresses |
| 84 | * should be generated and assigned to the environment variables |
| 85 | * "ethaddr" and "eth1addr". This is normally done during production. |
Haavard Skinnemoen | 58f4c26 | 2006-12-17 17:14:30 +0100 | [diff] [blame] | 86 | */ |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 87 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
Haavard Skinnemoen | 58f4c26 | 2006-12-17 17:14:30 +0100 | [diff] [blame] | 88 | |
Jon Loeliger | dcf1451 | 2007-07-09 21:48:26 -0500 | [diff] [blame] | 89 | /* |
| 90 | * BOOTP options |
| 91 | */ |
| 92 | #define CONFIG_BOOTP_SUBNETMASK |
| 93 | #define CONFIG_BOOTP_GATEWAY |
| 94 | |
Andreas Bießmann | 6639234 | 2015-02-06 23:06:50 +0100 | [diff] [blame] | 95 | /* generic board */ |
Andreas Bießmann | 6639234 | 2015-02-06 23:06:50 +0100 | [diff] [blame] | 96 | #define CONFIG_BOARD_EARLY_INIT_R |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 97 | |
Jon Loeliger | c5707f5 | 2007-07-04 22:31:42 -0500 | [diff] [blame] | 98 | /* |
| 99 | * Command line configuration. |
| 100 | */ |
Jon Loeliger | c5707f5 | 2007-07-04 22:31:42 -0500 | [diff] [blame] | 101 | #define CONFIG_CMD_JFFS2 |
Jon Loeliger | c5707f5 | 2007-07-04 22:31:42 -0500 | [diff] [blame] | 102 | |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 103 | #define CONFIG_ATMEL_USART |
| 104 | #define CONFIG_MACB |
| 105 | #define CONFIG_PORTMUX_PIO |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_NR_PIOS 5 |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 107 | #define CONFIG_SYS_HSDRAMC |
Sven Schnelle | 8aa9682 | 2011-10-21 14:49:25 +0200 | [diff] [blame] | 108 | #define CONFIG_GENERIC_ATMEL_MCI |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
| 111 | #define CONFIG_SYS_ICACHE_LINESZ 32 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 112 | |
| 113 | #define CONFIG_NR_DRAM_BANKS 1 |
| 114 | |
Andreas Bießmann | ab7344a | 2011-06-28 04:15:58 +0000 | [diff] [blame] | 115 | #define CONFIG_SYS_FLASH_CFI |
| 116 | #define CONFIG_FLASH_CFI_DRIVER |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 117 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 118 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
| 119 | #define CONFIG_SYS_FLASH_SIZE 0x800000 |
| 120 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 121 | #define CONFIG_SYS_MAX_FLASH_SECT 135 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 122 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
Andreas Bießmann | 71c2bf5 | 2011-04-18 04:12:44 +0000 | [diff] [blame] | 124 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
| 127 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE |
| 128 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 129 | |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 130 | #define CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 131 | #define CONFIG_ENV_SIZE 65536 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 135 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
Haavard Skinnemoen | abf19bf | 2006-11-20 15:53:10 +0100 | [diff] [blame] | 137 | |
Haavard Skinnemoen | 141cf5e | 2007-11-22 17:01:24 +0100 | [diff] [blame] | 138 | /* Allow 4MB for the kernel run-time image */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
| 140 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 141 | |
| 142 | /* Other configuration settings that shouldn't have to change all that often */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_CBSIZE 256 |
| 144 | #define CONFIG_SYS_MAXARGS 16 |
| 145 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
Andreas Bießmann | f40a5b7 | 2011-04-18 04:12:36 +0000 | [diff] [blame] | 146 | #define CONFIG_SYS_LONGHELP |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 147 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE |
| 149 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) |
| 150 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } |
Wolfgang Denk | 994ad96 | 2006-10-24 14:42:37 +0200 | [diff] [blame] | 151 | |
| 152 | #endif /* __CONFIG_H */ |