TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the Freescale MCF5475 board. |
| 3 | * |
| 4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * board/config.h - configuration options, board specific |
| 12 | */ |
| 13 | |
| 14 | #ifndef _M5475EVB_H |
| 15 | #define _M5475EVB_H |
| 16 | |
| 17 | /* |
| 18 | * High Level Configuration Options |
| 19 | * (easy to change) |
| 20 | */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 21 | |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 22 | #define CONFIG_MCFUART |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_UART_PORT (0) |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 24 | #define CONFIG_BAUDRATE 115200 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 25 | |
Alison Wang | 8f6d8f3 | 2015-02-12 18:33:15 +0800 | [diff] [blame] | 26 | #undef CONFIG_HW_WATCHDOG |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 27 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ |
| 28 | |
| 29 | /* Command line configuration */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 30 | #undef CONFIG_CMD_DATE |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 31 | #define CONFIG_CMD_PCI |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 32 | #define CONFIG_CMD_REGINFO |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 33 | |
| 34 | #define CONFIG_SLTTMR |
| 35 | |
| 36 | #define CONFIG_FSLDMAFEC |
| 37 | #ifdef CONFIG_FSLDMAFEC |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 38 | # define CONFIG_MII 1 |
TsiChung Liew | b316245 | 2008-03-30 01:22:13 -0500 | [diff] [blame] | 39 | # define CONFIG_MII_INIT 1 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 40 | # define CONFIG_HAS_ETH1 |
| 41 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | # define CONFIG_SYS_DMA_USE_INTSRAM 1 |
| 43 | # define CONFIG_SYS_DISCOVER_PHY |
| 44 | # define CONFIG_SYS_RX_ETH_BUFFER 32 |
| 45 | # define CONFIG_SYS_TX_ETH_BUFFER 48 |
| 46 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 47 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | # define CONFIG_SYS_FEC0_PINMUX 0 |
| 49 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE |
| 50 | # define CONFIG_SYS_FEC1_PINMUX 0 |
| 51 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 52 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 53 | # define MCFFEC_TOUT_LOOP 50000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 55 | # ifndef CONFIG_SYS_DISCOVER_PHY |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 56 | # define FECDUPLEX FULL |
| 57 | # define FECSPEED _100BASET |
| 58 | # else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 60 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 61 | # endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 62 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 63 | |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 64 | # define CONFIG_IPADDR 192.162.1.2 |
| 65 | # define CONFIG_NETMASK 255.255.255.0 |
| 66 | # define CONFIG_SERVERIP 192.162.1.1 |
| 67 | # define CONFIG_GATEWAYIP 192.162.1.1 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 68 | |
| 69 | #endif |
| 70 | |
| 71 | #ifdef CONFIG_CMD_USB |
| 72 | # define CONFIG_USB_OHCI_NEW |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 73 | |
| 74 | # ifndef CONFIG_CMD_PCI |
| 75 | # define CONFIG_CMD_PCI |
| 76 | # endif |
| 77 | # define CONFIG_PCI_OHCI |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 78 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | # undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
| 80 | # undef CONFIG_SYS_USB_OHCI_CPU_INIT |
| 81 | # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
| 82 | # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" |
| 83 | # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 84 | #endif |
| 85 | |
| 86 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_I2C |
| 88 | #define CONFIG_SYS_I2C_FSL |
| 89 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 |
| 90 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 91 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 93 | |
| 94 | /* PCI */ |
| 95 | #ifdef CONFIG_CMD_PCI |
TsiChung Liew | 521f97b | 2008-03-30 01:19:06 -0500 | [diff] [blame] | 96 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 97 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 98 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 99 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 |
| 101 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS |
| 102 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 103 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_PCI_IO_BUS 0x71000000 |
| 105 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS |
| 106 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 107 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 |
| 109 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS |
| 110 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 111 | #endif |
| 112 | |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 113 | #define CONFIG_UDP_CHECKSUM |
| 114 | |
| 115 | #ifdef CONFIG_MCFFEC |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 116 | # define CONFIG_IPADDR 192.162.1.2 |
| 117 | # define CONFIG_NETMASK 255.255.255.0 |
| 118 | # define CONFIG_SERVERIP 192.162.1.1 |
| 119 | # define CONFIG_GATEWAYIP 192.162.1.1 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 120 | #endif /* FEC_ENET */ |
| 121 | |
| 122 | #define CONFIG_HOSTNAME M547xEVB |
| 123 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 124 | "netdev=eth0\0" \ |
| 125 | "loadaddr=10000\0" \ |
| 126 | "u-boot=u-boot.bin\0" \ |
| 127 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 128 | "upd=run load; run prog\0" \ |
| 129 | "prog=prot off bank 1;" \ |
Jason Jin | ded4eb4 | 2011-08-19 10:10:40 +0800 | [diff] [blame] | 130 | "era ff800000 ff83ffff;" \ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 131 | "cp.b ${loadaddr} ff800000 ${filesize};"\ |
| 132 | "save\0" \ |
| 133 | "" |
| 134 | |
| 135 | #define CONFIG_PRAM 512 /* 512 KB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 137 | |
| 138 | #ifdef CONFIG_CMD_KGDB |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 140 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 142 | #endif |
| 143 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 145 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 146 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 147 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 148 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK |
| 150 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 151 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #define CONFIG_SYS_MBAR 0xF0000000 |
| 153 | #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) |
| 154 | #define CONFIG_SYS_INTSRAMSZ 0x8000 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 155 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 157 | |
| 158 | /* |
| 159 | * Low Level Configuration Settings |
| 160 | * (address mappings, register initial values, etc.) |
| 161 | * You should know what you are doing if you make changes here. |
| 162 | */ |
| 163 | /*----------------------------------------------------------------------- |
| 164 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 165 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_INIT_RAM_CTRL 0x21 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ |
| 171 | #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 174 | |
| 175 | /*----------------------------------------------------------------------- |
| 176 | * Start addresses for the final memory configuration |
| 177 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 179 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 181 | #define CONFIG_SYS_SDRAM_CFG1 0x73711630 |
| 182 | #define CONFIG_SYS_SDRAM_CFG2 0x46770000 |
| 183 | #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 |
| 184 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 |
| 185 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 |
| 186 | #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA |
| 187 | #ifdef CONFIG_SYS_DRAMSZ1 |
| 188 | # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 189 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 191 | #endif |
| 192 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
| 194 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 195 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 197 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 198 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 200 | |
Jason Jin | ded4eb4 | 2011-08-19 10:10:40 +0800 | [diff] [blame] | 201 | /* Reserve 256 kB for malloc() */ |
| 202 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 203 | /* |
| 204 | * For booting Linux, the board info and command line data |
| 205 | * have to be in the first 8 MB of memory, since this is |
| 206 | * the maximum mapped by the Linux kernel during initialization ?? |
| 207 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 209 | |
| 210 | /*----------------------------------------------------------------------- |
| 211 | * FLASH organization |
| 212 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_FLASH_CFI |
| 214 | #ifdef CONFIG_SYS_FLASH_CFI |
| 215 | # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 216 | # define CONFIG_FLASH_CFI_DRIVER 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 217 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 218 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
| 219 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
| 220 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 221 | #ifdef CONFIG_SYS_NOR1SZ |
| 222 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 223 | # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) |
| 224 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 225 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 227 | # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 228 | #endif |
| 229 | #endif |
| 230 | |
| 231 | /* Configuration for environment |
Jason Jin | ded4eb4 | 2011-08-19 10:10:40 +0800 | [diff] [blame] | 232 | * Environment is not embedded in u-boot but at offset 0x40000 on the flash. |
| 233 | * First time runing may have env crc error warning if there is |
| 234 | * no correct environment on the flash. |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 235 | */ |
Jason Jin | ded4eb4 | 2011-08-19 10:10:40 +0800 | [diff] [blame] | 236 | #define CONFIG_ENV_OFFSET 0x40000 |
| 237 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 238 | #define CONFIG_ENV_IS_IN_FLASH 1 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 239 | |
| 240 | /*----------------------------------------------------------------------- |
| 241 | * Cache Configuration |
| 242 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 244 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 245 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 246 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 247 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 248 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 249 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ |
| 250 | CF_CACR_IDCM) |
| 251 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) |
| 252 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ |
| 253 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 254 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 255 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ |
| 256 | CF_CACR_IEC | CF_CACR_ICINVA) |
| 257 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ |
| 258 | CF_CACR_DEC | CF_CACR_DDCM_P | \ |
| 259 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) |
| 260 | |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 261 | /*----------------------------------------------------------------------- |
| 262 | * Chipselect bank definitions |
| 263 | */ |
| 264 | /* |
| 265 | * CS0 - NOR Flash 1, 2, 4, or 8MB |
| 266 | * CS1 - NOR Flash |
| 267 | * CS2 - Available |
| 268 | * CS3 - Available |
| 269 | * CS4 - Available |
| 270 | * CS5 - Available |
| 271 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 272 | #define CONFIG_SYS_CS0_BASE 0xFF800000 |
| 273 | #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) |
| 274 | #define CONFIG_SYS_CS0_CTRL 0x00101980 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 275 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | #ifdef CONFIG_SYS_NOR1SZ |
| 277 | #define CONFIG_SYS_CS1_BASE 0xE0000000 |
| 278 | #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) |
| 279 | #define CONFIG_SYS_CS1_CTRL 0x00101D80 |
TsiChungLiew | 8cb946d | 2008-01-15 14:15:46 -0600 | [diff] [blame] | 280 | #endif |
| 281 | |
| 282 | #endif /* _M5475EVB_H */ |