| maxims@google.com | f57bd00 | 2017-01-18 13:44:55 -0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2016 Google, Inc |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/arch/wdt.h> |
| 10 | #include <linux/err.h> |
| 11 | |
| 12 | void wdt_stop(struct ast_wdt *wdt) |
| 13 | { |
| 14 | clrbits_le32(&wdt->ctrl, WDT_CTRL_EN); |
| 15 | } |
| 16 | |
| 17 | void wdt_start(struct ast_wdt *wdt, u32 timeout) |
| 18 | { |
| 19 | writel(timeout, &wdt->counter_reload_val); |
| 20 | writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart); |
| 21 | /* |
| 22 | * Setting CLK1MHZ bit is just for compatibility with ast2400 part. |
| 23 | * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is |
| 24 | * read-only |
| 25 | */ |
| 26 | setbits_le32(&wdt->ctrl, |
| 27 | WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ); |
| 28 | } |
| 29 | |
| 30 | struct ast_wdt *ast_get_wdt(u8 wdt_number) |
| 31 | { |
| 32 | if (wdt_number > CONFIG_WDT_NUM - 1) |
| 33 | return ERR_PTR(-EINVAL); |
| 34 | |
| 35 | return (struct ast_wdt *)(WDT_BASE + |
| 36 | sizeof(struct ast_wdt) * wdt_number); |
| 37 | } |
| 38 | |
| 39 | int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask) |
| 40 | { |
| 41 | #ifdef CONFIG_ASPEED_AST2500 |
| 42 | if (!mask) |
| 43 | return -EINVAL; |
| 44 | |
| 45 | writel(mask, &wdt->reset_mask); |
| 46 | clrbits_le32(&wdt->ctrl, |
| 47 | WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT); |
| 48 | wdt_start(wdt, 1); |
| 49 | |
| 50 | /* Wait for WDT to reset */ |
| 51 | while (readl(&wdt->ctrl) & WDT_CTRL_EN) |
| 52 | ; |
| 53 | wdt_stop(wdt); |
| 54 | |
| 55 | return 0; |
| 56 | #else |
| 57 | return -EINVAL; |
| 58 | #endif |
| 59 | } |