| wdenk | a21ad7b | 2005-05-19 22:39:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify |
| 3 | * it under the terms of the GNU General Public License as published by |
| 4 | * the Free Software Foundation; either version 2 of the License, or |
| 5 | * (at your option) any later version. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * You should have received a copy of the GNU General Public License |
| 13 | * along with this program; if not, write to the Free Software |
| 14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 15 | */ |
| 16 | #ifndef __address_h |
| 17 | #define __address_h 1 |
| 18 | |
| 19 | #define KS8695_SDRAM_START 0x00000000 |
| 20 | #define KS8695_SDRAM_SIZE 0x01000000 |
| 21 | #define KS8695_MEM_SIZE KS8695_SDRAM_SIZE |
| 22 | #define KS8695_MEM_START KS8695_SDRAM_START |
| 23 | |
| 24 | #define KS8695_PCMCIA_IO_BASE 0x03800000 |
| 25 | #define KS8695_PCMCIA_IO_SIZE 0x00040000 |
| 26 | |
| 27 | #define KS8695_IO_BASE 0x03FF0000 |
| 28 | #define KS8695_IO_SIZE 0x00010000 |
| 29 | |
| 30 | #define KS8695_SYSTEN_CONFIG 0x00 |
| 31 | #define KS8695_SYSTEN_BUS_CLOCK 0x04 |
| 32 | |
| 33 | #define KS8695_FLASH_START 0x02800000 |
| 34 | #define KS8695_FLASH_SIZE 0x00400000 |
| 35 | |
| 36 | /*i/o control registers offset difinitions*/ |
| 37 | #define KS8695_IO_CTRL0 0x4000 |
| 38 | #define KS8695_IO_CTRL1 0x4004 |
| 39 | #define KS8695_IO_CTRL2 0x4008 |
| 40 | #define KS8695_IO_CTRL3 0x400C |
| 41 | |
| 42 | /*memory control registers offset difinitions*/ |
| 43 | #define KS8695_MEM_CTRL0 0x4010 |
| 44 | #define KS8695_MEM_CTRL1 0x4014 |
| 45 | #define KS8695_MEM_CTRL2 0x4018 |
| 46 | #define KS8695_MEM_CTRL3 0x401C |
| 47 | #define KS8695_MEM_GENERAL 0x4020 |
| 48 | #define KS8695_SDRAM_CTRL0 0x4030 |
| 49 | #define KS8695_SDRAM_CTRL1 0x4034 |
| 50 | #define KS8695_SDRAM_GENERAL 0x4038 |
| 51 | #define KS8695_SDRAM_BUFFER 0x403C |
| 52 | #define KS8695_SDRAM_REFRESH 0x4040 |
| 53 | |
| 54 | /*WAN control registers offset difinitions*/ |
| 55 | #define KS8695_WAN_DMA_TX 0x6000 |
| 56 | #define KS8695_WAN_DMA_RX 0x6004 |
| 57 | #define KS8695_WAN_DMA_TX_START 0x6008 |
| 58 | #define KS8695_WAN_DMA_RX_START 0x600C |
| 59 | #define KS8695_WAN_TX_LIST 0x6010 |
| 60 | #define KS8695_WAN_RX_LIST 0x6014 |
| 61 | #define KS8695_WAN_MAC_LOW 0x6018 |
| 62 | #define KS8695_WAN_MAC_HIGH 0x601C |
| 63 | #define KS8695_WAN_MAC_ELOW 0x6080 |
| 64 | #define KS8695_WAN_MAC_EHIGH 0x6084 |
| 65 | |
| 66 | /*LAN control registers offset difinitions*/ |
| 67 | #define KS8695_LAN_DMA_TX 0x8000 |
| 68 | #define KS8695_LAN_DMA_RX 0x8004 |
| 69 | #define KS8695_LAN_DMA_TX_START 0x8008 |
| 70 | #define KS8695_LAN_DMA_RX_START 0x800C |
| 71 | #define KS8695_LAN_TX_LIST 0x8010 |
| 72 | #define KS8695_LAN_RX_LIST 0x8014 |
| 73 | #define KS8695_LAN_MAC_LOW 0x8018 |
| 74 | #define KS8695_LAN_MAC_HIGH 0x801C |
| 75 | #define KS8695_LAN_MAC_ELOW 0X8080 |
| 76 | #define KS8695_LAN_MAC_EHIGH 0X8084 |
| 77 | |
| 78 | /*HPNA control registers offset difinitions*/ |
| 79 | #define KS8695_HPNA_DMA_TX 0xA000 |
| 80 | #define KS8695_HPNA_DMA_RX 0xA004 |
| 81 | #define KS8695_HPNA_DMA_TX_START 0xA008 |
| 82 | #define KS8695_HPNA_DMA_RX_START 0xA00C |
| 83 | #define KS8695_HPNA_TX_LIST 0xA010 |
| 84 | #define KS8695_HPNA_RX_LIST 0xA014 |
| 85 | #define KS8695_HPNA_MAC_LOW 0xA018 |
| 86 | #define KS8695_HPNA_MAC_HIGH 0xA01C |
| 87 | #define KS8695_HPNA_MAC_ELOW 0xA080 |
| 88 | #define KS8695_HPNA_MAC_EHIGH 0xA084 |
| 89 | |
| 90 | /*UART control registers offset difinitions*/ |
| 91 | #define KS8695_UART_RX_BUFFER 0xE000 |
| 92 | #define KS8695_UART_TX_HOLDING 0xE004 |
| 93 | |
| 94 | #define KS8695_UART_FIFO_CTRL 0xE008 |
| 95 | #define KS8695_UART_FIFO_TRIG01 0x00 |
| 96 | #define KS8695_UART_FIFO_TRIG04 0x80 |
| 97 | #define KS8695_UART_FIFO_TXRST 0x03 |
| 98 | #define KS8695_UART_FIFO_RXRST 0x02 |
| 99 | #define KS8695_UART_FIFO_FEN 0x01 |
| 100 | |
| 101 | #define KS8695_UART_LINE_CTRL 0xE00C |
| 102 | #define KS8695_UART_LINEC_BRK 0x40 |
| 103 | #define KS8695_UART_LINEC_EPS 0x10 |
| 104 | #define KS8695_UART_LINEC_PEN 0x08 |
| 105 | #define KS8695_UART_LINEC_STP2 0x04 |
| 106 | #define KS8695_UART_LINEC_WLEN8 0x03 |
| 107 | #define KS8695_UART_LINEC_WLEN7 0x02 |
| 108 | #define KS8695_UART_LINEC_WLEN6 0x01 |
| 109 | #define KS8695_UART_LINEC_WLEN5 0x00 |
| 110 | |
| 111 | #define KS8695_UART_MODEM_CTRL 0xE010 |
| 112 | #define KS8695_UART_MODEMC_RTS 0x02 |
| 113 | #define KS8695_UART_MODEMC_DTR 0x01 |
| 114 | |
| 115 | #define KS8695_UART_LINE_STATUS 0xE014 |
| 116 | #define KS8695_UART_LINES_TXFE 0x20 |
| 117 | #define KS8695_UART_LINES_BE 0x10 |
| 118 | #define KS8695_UART_LINES_FE 0x08 |
| 119 | #define KS8695_UART_LINES_PE 0x04 |
| 120 | #define KS8695_UART_LINES_OE 0x02 |
| 121 | #define KS8695_UART_LINES_RXFE 0x01 |
| 122 | #define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) |
| 123 | |
| 124 | #define KS8695_UART_MODEM_STATUS 0xE018 |
| 125 | #define KS8695_UART_MODEM_DCD 0x80 |
| 126 | #define KS8695_UART_MODEM_DSR 0x20 |
| 127 | #define KS8695_UART_MODEM_CTS 0x10 |
| 128 | #define KS8695_UART_MODEM_DDCD 0x08 |
| 129 | #define KS8695_UART_MODEM_DDSR 0x02 |
| 130 | #define KS8695_UART_MODEM_DCTS 0x01 |
| 131 | #define UART8695_MODEM_ANY 0xFF |
| 132 | |
| 133 | #define KS8695_UART_DIVISOR 0xE01C |
| 134 | #define KS8695_UART_STATUS 0xE020 |
| 135 | |
| 136 | /*Interrupt controlller registers offset difinitions*/ |
| 137 | #define KS8695_INT_CONTL 0xE200 |
| 138 | #define KS8695_INT_ENABLE 0xE204 |
| 139 | #define KS8695_INT_ENABLE_MODEM 0x0800 |
| 140 | #define KS8695_INT_ENABLE_ERR 0x0400 |
| 141 | #define KS8695_INT_ENABLE_RX 0x0200 |
| 142 | #define KS8695_INT_ENABLE_TX 0x0100 |
| 143 | |
| 144 | #define KS8695_INT_STATUS 0xE208 |
| 145 | #define KS8695_INT_WAN_PRIORITY 0xE20C |
| 146 | #define KS8695_INT_HPNA_PRIORITY 0xE210 |
| 147 | #define KS8695_INT_LAN_PRIORITY 0xE214 |
| 148 | #define KS8695_INT_TIMER_PRIORITY 0xE218 |
| 149 | #define KS8695_INT_UART_PRIORITY 0xE21C |
| 150 | #define KS8695_INT_EXT_PRIORITY 0xE220 |
| 151 | #define KS8695_INT_CHAN_PRIORITY 0xE224 |
| 152 | #define KS8695_INT_BUSERROR_PRO 0xE228 |
| 153 | #define KS8695_INT_MASK_STATUS 0xE22C |
| 154 | #define KS8695_FIQ_PEND_PRIORITY 0xE230 |
| 155 | #define KS8695_IRQ_PEND_PRIORITY 0xE234 |
| 156 | |
| 157 | /*timer registers offset difinitions*/ |
| 158 | #define KS8695_TIMER_CTRL 0xE400 |
| 159 | #define KS8695_TIMER1 0xE404 |
| 160 | #define KS8695_TIMER0 0xE408 |
| 161 | #define KS8695_TIMER1_PCOUNT 0xE40C |
| 162 | #define KS8695_TIMER0_PCOUNT 0xE410 |
| 163 | |
| 164 | /*GPIO registers offset difinitions*/ |
| 165 | #define KS8695_GPIO_MODE 0xE600 |
| 166 | #define KS8695_GPIO_CTRL 0xE604 |
| 167 | #define KS8695_GPIO_DATA 0xE608 |
| 168 | |
| 169 | /*SWITCH registers offset difinitions*/ |
| 170 | #define KS8695_SWITCH_CTRL0 0xE800 |
| 171 | #define KS8695_SWITCH_CTRL1 0xE804 |
| 172 | #define KS8695_SWITCH_PORT1 0xE808 |
| 173 | #define KS8695_SWITCH_PORT2 0xE80C |
| 174 | #define KS8695_SWITCH_PORT3 0xE810 |
| 175 | #define KS8695_SWITCH_PORT4 0xE814 |
| 176 | #define KS8695_SWITCH_PORT5 0xE818 |
| 177 | #define KS8695_SWITCH_AUTO0 0xE81C |
| 178 | #define KS8695_SWITCH_AUTO1 0xE820 |
| 179 | #define KS8695_SWITCH_LUE_CTRL 0xE824 |
| 180 | #define KS8695_SWITCH_LUE_HIGH 0xE828 |
| 181 | #define KS8695_SWITCH_LUE_LOW 0xE82C |
| 182 | #define KS8695_SWITCH_ADVANCED 0xE830 |
| 183 | |
| 184 | #define KS8695_SWITCH_LPPM12 0xE874 |
| 185 | #define KS8695_SWITCH_LPPM34 0xE878 |
| 186 | |
| 187 | /*host communication registers difinitions*/ |
| 188 | #define KS8695_DSCP_HIGH 0xE834 |
| 189 | #define KS8695_DSCP_LOW 0xE838 |
| 190 | #define KS8695_SWITCH_MAC_HIGH 0xE83C |
| 191 | #define KS8695_SWITCH_MAC_LOW 0xE840 |
| 192 | |
| 193 | /*miscellaneours registers difinitions*/ |
| 194 | #define KS8695_MANAGE_COUNTER 0xE844 |
| 195 | #define KS8695_MANAGE_DATA 0xE848 |
| 196 | #define KS8695_LAN12_POWERMAGR 0xE84C |
| 197 | #define KS8695_LAN34_POWERMAGR 0xE850 |
| 198 | |
| 199 | #define KS8695_DEVICE_ID 0xEA00 |
| 200 | #define KS8695_REVISION_ID 0xEA04 |
| 201 | |
| 202 | #define KS8695_MISC_CONTROL 0xEA08 |
| 203 | #define KS8695_WAN_CONTROL 0xEA0C |
| 204 | #define KS8695_WAN_POWERMAGR 0xEA10 |
| 205 | #define KS8695_WAN_PHY_CONTROL 0xEA14 |
| 206 | #define KS8695_WAN_PHY_STATUS 0xEA18 |
| 207 | |
| 208 | /* bus clock definitions*/ |
| 209 | #define KS8695_BUS_CLOCK_125MHZ 0x0 |
| 210 | #define KS8695_BUS_CLOCK_100MHZ 0x1 |
| 211 | #define KS8695_BUS_CLOCK_62MHZ 0x2 |
| 212 | #define KS8695_BUS_CLOCK_50MHZ 0x3 |
| 213 | #define KS8695_BUS_CLOCK_41MHZ 0x4 |
| 214 | #define KS8695_BUS_CLOCK_33MHZ 0x5 |
| 215 | #define KS8695_BUS_CLOCK_31MHZ 0x6 |
| 216 | #define KS8695_BUS_CLOCK_25MHZ 0x7 |
| 217 | |
| 218 | /* ------------------------------------------------------------------------------- |
| 219 | * definations for IRQ |
| 220 | * -------------------------------------------------------------------------------*/ |
| 221 | |
| 222 | #define KS8695_INT_EXT_INT0 2 |
| 223 | #define KS8695_INT_EXT_INT1 3 |
| 224 | #define KS8695_INT_EXT_INT2 4 |
| 225 | #define KS8695_INT_EXT_INT3 5 |
| 226 | #define KS8695_INT_TIMERINT0 6 |
| 227 | #define KS8695_INT_TIMERINT1 7 |
| 228 | #define KS8695_INT_UART_TX 8 |
| 229 | #define KS8695_INT_UART_RX 9 |
| 230 | #define KS8695_INT_UART_LINE_ERR 10 |
| 231 | #define KS8695_INT_UART_MODEMS 11 |
| 232 | #define KS8695_INT_LAN_STOP_RX 12 |
| 233 | #define KS8695_INT_LAN_STOP_TX 13 |
| 234 | #define KS8695_INT_LAN_BUF_RX_STATUS 14 |
| 235 | #define KS8695_INT_LAN_BUF_TX_STATUS 15 |
| 236 | #define KS8695_INT_LAN_RX_STATUS 16 |
| 237 | #define KS8695_INT_LAN_TX_STATUS 17 |
| 238 | #define KS8695_INT_HPAN_STOP_RX 18 |
| 239 | #define KS8695_INT_HPNA_STOP_TX 19 |
| 240 | #define KS8695_INT_HPNA_BUF_RX_STATUS 20 |
| 241 | #define KS8695_INT_HPNA_BUF_TX_STATUS 21 |
| 242 | #define KS8695_INT_HPNA_RX_STATUS 22 |
| 243 | #define KS8695_INT_HPNA_TX_STATUS 23 |
| 244 | #define KS8695_INT_BUS_ERROR 24 |
| 245 | #define KS8695_INT_WAN_STOP_RX 25 |
| 246 | #define KS8695_INT_WAN_STOP_TX 26 |
| 247 | #define KS8695_INT_WAN_BUF_RX_STATUS 27 |
| 248 | #define KS8695_INT_WAN_BUF_TX_STATUS 28 |
| 249 | #define KS8695_INT_WAN_RX_STATUS 29 |
| 250 | #define KS8695_INT_WAN_TX_STATUS 30 |
| 251 | |
| 252 | #define KS8695_INT_UART KS8695_INT_UART_TX |
| 253 | |
| 254 | /* ------------------------------------------------------------------------------- |
| 255 | * Interrupt bit positions |
| 256 | * |
| 257 | * ------------------------------------------------------------------------------- |
| 258 | */ |
| 259 | |
| 260 | #define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) |
| 261 | #define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) |
| 262 | #define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) |
| 263 | #define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) |
| 264 | #define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) |
| 265 | #define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) |
| 266 | #define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) |
| 267 | #define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) |
| 268 | #define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) |
| 269 | #define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) |
| 270 | #define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) |
| 271 | #define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) |
| 272 | #define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) |
| 273 | #define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) |
| 274 | #define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) |
| 275 | #define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) |
| 276 | #define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) |
| 277 | #define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) |
| 278 | #define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) |
| 279 | #define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS |
| 280 | #define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) |
| 281 | #define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) |
| 282 | #define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) |
| 283 | #define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) |
| 284 | #define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) |
| 285 | #define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) |
| 286 | #define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) |
| 287 | #define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) |
| 288 | #define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) |
| 289 | |
| 290 | #define KS8695_SC_VALID_INT 0xFFFFFFFF |
| 291 | #define MAXIRQNUM 31 |
| 292 | |
| 293 | /* |
| 294 | * Timer definitions |
| 295 | * |
| 296 | * Use timer 1 & 2 |
| 297 | * (both run at 25MHz). |
| 298 | * |
| 299 | */ |
| 300 | #define TICKS_PER_uSEC 25 |
| 301 | #define mSEC_1 1000 |
| 302 | #define mSEC_10 (mSEC_1 * 10) |
| 303 | |
| 304 | #endif |
| 305 | |
| 306 | /* END */ |