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git01.mediatek.com / filogic / uboot / d0f9c7b3f3810125c5e7336a527ed97b54ab6451 / . / arch / arm / mach-k3 / j721e / clk-data.c
blob: 5ab795139e1d46ef52e4347ad11ccae916ccf04f [file] [log] [blame]
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * J721E specific clock platform data
4 *
Dave Gerlach0949b992021-09-07 17:16:56 -0500[diff] [blame]5 * This file is auto generated. Please do not hand edit and report any issues
6 * to Dave Gerlach <d-gerlach@ti.com>.
7 *
8 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]9 */
Dave Gerlach0949b992021-09-07 17:16:56 -0500[diff] [blame]10
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]11#include <linux/clk-provider.h>
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]12#include "k3-clk.h"
13
14static const char * const gluelogic_hfosc0_clkout_parents[] = {
15 "osc_19_2_mhz",
16 "osc_20_mhz",
17 "osc_24_mhz",
18 "osc_25_mhz",
19 "osc_26_mhz",
20 "osc_27_mhz",
21};
22
23static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
24 "board_0_mcu_ospi0_dqs_out",
25 "fss_mcu_0_ospi_0_ospi_oclk_clk",
26};
27
28static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
29 "board_0_mcu_ospi1_dqs_out",
30 "fss_mcu_0_ospi_1_ospi_oclk_clk",
31};
32
33static const char * const wkup_fref_clksel_out0_parents[] = {
34 "gluelogic_hfosc0_clkout",
35 "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
36};
37
38static const char * const main_pll_hfosc_sel_out1_parents[] = {
39 "gluelogic_hfosc0_clkout",
40 "board_0_hfosc1_clk_out",
41};
42
43static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
44 "wkup_fref_clksel_out0",
45 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
46};
47
48static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
49 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
50 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
51};
52
53static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
54 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
55 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
56};
57
58static const char * const mcuusart_clk_sel_out0_parents[] = {
59 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
60 "postdiv3_16fft_main_1_hsdivout5_clk",
61};
62
63static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
64 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
65 "gluelogic_hfosc0_clkout",
66};
67
68static const char * const main_pll25_hfosc_sel_out0_parents[] = {
69 "gluelogic_hfosc0_clkout",
70 "board_0_hfosc1_clk_out",
71};
72
73static const char * const main_pll_hfosc_sel_out0_parents[] = {
74 "gluelogic_hfosc0_clkout",
75 "board_0_hfosc1_clk_out",
76};
77
78static const char * const main_pll_hfosc_sel_out12_parents[] = {
79 "gluelogic_hfosc0_clkout",
80 "board_0_hfosc1_clk_out",
81};
82
83static const char * const main_pll_hfosc_sel_out13_parents[] = {
84 "gluelogic_hfosc0_clkout",
85 "board_0_hfosc1_clk_out",
86};
87
88static const char * const main_pll_hfosc_sel_out14_parents[] = {
89 "gluelogic_hfosc0_clkout",
90 "board_0_hfosc1_clk_out",
91};
92
93static const char * const main_pll_hfosc_sel_out15_parents[] = {
94 "gluelogic_hfosc0_clkout",
95 "board_0_hfosc1_clk_out",
96};
97
98static const char * const main_pll_hfosc_sel_out16_parents[] = {
99 "gluelogic_hfosc0_clkout",
100 "board_0_hfosc1_clk_out",
101};
102
103static const char * const main_pll_hfosc_sel_out17_parents[] = {
104 "gluelogic_hfosc0_clkout",
105 "board_0_hfosc1_clk_out",
106};
107
108static const char * const main_pll_hfosc_sel_out18_parents[] = {
109 "gluelogic_hfosc0_clkout",
110 "board_0_hfosc1_clk_out",
111};
112
113static const char * const main_pll_hfosc_sel_out19_parents[] = {
114 "gluelogic_hfosc0_clkout",
115 "board_0_hfosc1_clk_out",
116};
117
118static const char * const main_pll_hfosc_sel_out2_parents[] = {
119 "gluelogic_hfosc0_clkout",
120 "board_0_hfosc1_clk_out",
121};
122
123static const char * const main_pll_hfosc_sel_out23_parents[] = {
124 "gluelogic_hfosc0_clkout",
125 "board_0_hfosc1_clk_out",
126};
127
128static const char * const main_pll_hfosc_sel_out3_parents[] = {
129 "gluelogic_hfosc0_clkout",
130 "board_0_hfosc1_clk_out",
131};
132
133static const char * const main_pll_hfosc_sel_out4_parents[] = {
134 "gluelogic_hfosc0_clkout",
135 "board_0_hfosc1_clk_out",
136};
137
138static const char * const main_pll_hfosc_sel_out5_parents[] = {
139 "gluelogic_hfosc0_clkout",
140 "board_0_hfosc1_clk_out",
141};
142
143static const char * const main_pll_hfosc_sel_out6_parents[] = {
144 "gluelogic_hfosc0_clkout",
145 "board_0_hfosc1_clk_out",
146};
147
148static const char * const main_pll_hfosc_sel_out7_parents[] = {
149 "gluelogic_hfosc0_clkout",
150 "board_0_hfosc1_clk_out",
151};
152
153static const char * const main_pll_hfosc_sel_out8_parents[] = {
154 "gluelogic_hfosc0_clkout",
155 "board_0_hfosc1_clk_out",
156};
157
158static const char * const usb0_refclk_sel_out0_parents[] = {
159 "gluelogic_hfosc0_clkout",
160 "board_0_hfosc1_clk_out",
161};
162
163static const char * const usb1_refclk_sel_out0_parents[] = {
164 "gluelogic_hfosc0_clkout",
165 "board_0_hfosc1_clk_out",
166};
167
168static const char * const wkup_obsclk_mux_out0_parents[] = {
169 "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
170 NULL,
171 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
172 "hsdiv1_16fft_mcu_0_hsdivout0_clk",
173 "hsdiv4_16fft_mcu_1_hsdivout1_clk",
174 "hsdiv4_16fft_mcu_1_hsdivout2_clk",
175 "hsdiv4_16fft_mcu_1_hsdivout3_clk",
176 "hsdiv4_16fft_mcu_1_hsdivout4_clk",
177 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
178 "j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
179 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
180 "hsdiv4_16fft_mcu_2_hsdivout2_clk",
181 "hsdiv4_16fft_mcu_2_hsdivout3_clk",
182 "hsdiv4_16fft_mcu_2_hsdivout4_clk",
183 "gluelogic_hfosc0_clkout",
184 "gluelogic_lpxosc_clkout",
185};
186
187static const char * const main_pll15_xref_sel_out0_parents[] = {
188 "main_pll_hfosc_sel_out15",
189 "board_0_ext_refclk1_out",
190};
191
192static const char * const main_pll24_hfosc_sel_out0_parents[] = {
193 "gluelogic_hfosc0_clkout",
194 "board_0_mlb0_mlbcp_out",
195};
196
197static const char * const main_pll4_xref_sel_out0_parents[] = {
198 "main_pll_hfosc_sel_out4",
199 "board_0_ext_refclk1_out",
200};
201
202static const char * const mcu_clkout_mux_out0_parents[] = {
203 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
204 "hsdiv4_16fft_mcu_2_hsdivout0_clk",
205};
206
207static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
208 "main_pll_hfosc_sel_out0",
209 "hsdiv4_16fft_main_0_hsdivout0_clk",
210};
211
212static const char * const mcu_obsclk_outmux_out0_parents[] = {
213 "mcu_obsclk_div_out0",
214 "gluelogic_hfosc0_clkout",
215};
216
217static const char * const obsclk1_mux_out0_parents[] = {
218 "hsdiv0_16fft_main_7_hsdivout0_clk",
219 "hsdiv0_16fft_main_8_hsdivout0_clk",
220 "hsdiv3_16fft_main_13_hsdivout0_clk",
221 NULL,
222};
223
224static const char * const clkout_mux_out0_parents[] = {
225 "hsdiv4_16fft_main_3_hsdivout0_clk",
226 "hsdiv4_16fft_main_3_hsdivout0_clk",
227};
228
229static const char * const emmcsd_refclk_sel_out0_parents[] = {
230 "hsdiv4_16fft_main_0_hsdivout2_clk",
231 "hsdiv4_16fft_main_1_hsdivout2_clk",
232 "hsdiv4_16fft_main_2_hsdivout2_clk",
233 "hsdiv4_16fft_main_3_hsdivout2_clk",
234};
235
236static const char * const emmcsd_refclk_sel_out1_parents[] = {
237 "hsdiv4_16fft_main_0_hsdivout2_clk",
238 "hsdiv4_16fft_main_1_hsdivout2_clk",
239 "hsdiv4_16fft_main_2_hsdivout2_clk",
240 "hsdiv4_16fft_main_3_hsdivout2_clk",
241};
242
243static const char * const gtc_clk_mux_out0_parents[] = {
244 "hsdiv4_16fft_main_3_hsdivout1_clk",
245 "postdiv3_16fft_main_0_hsdivout6_clk",
246 "board_0_mcu_cpts0_rft_clk_out",
247 "board_0_cpts0_rft_clk_out",
248 "board_0_mcu_ext_refclk0_out",
249 "board_0_ext_refclk1_out",
250 NULL,
251 NULL,
252 NULL,
253 NULL,
254 NULL,
255 NULL,
256 NULL,
257 NULL,
258 "hsdiv4_16fft_mcu_2_hsdivout1_clk",
259 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
260};
261
262static const char * const gpmc_fclk_sel_out0_parents[] = {
263 "hsdiv4_16fft_main_0_hsdivout3_clk",
264 "hsdiv4_16fft_main_2_hsdivout1_clk",
265 "hsdiv4_16fft_main_2_hsdivout1_clk",
266 "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
267};
268
269static const char * const mcasp_ahclko_mux_out0_parents[] = {
270 NULL,
271 NULL,
272 NULL,
273 NULL,
274 NULL,
275 NULL,
276 NULL,
277 NULL,
278 NULL,
279 NULL,
280 NULL,
281 NULL,
282 NULL,
283 NULL,
284 NULL,
285 NULL,
286 NULL,
287 NULL,
288 NULL,
289 NULL,
290 NULL,
291 NULL,
292 NULL,
293 NULL,
294 NULL,
295 NULL,
296 NULL,
297 NULL,
298 "hsdiv3_16fft_main_4_hsdivout2_clk",
299 "hsdiv3_16fft_main_15_hsdivout2_clk",
300 NULL,
301 NULL,
302 "board_0_audio_ext_refclk0_out",
303};
304
305static const char * const mcasp_ahclko_mux_out1_parents[] = {
306 NULL,
307 NULL,
308 NULL,
309 NULL,
310 NULL,
311 NULL,
312 NULL,
313 NULL,
314 NULL,
315 NULL,
316 NULL,
317 NULL,
318 NULL,
319 NULL,
320 NULL,
321 NULL,
322 NULL,
323 NULL,
324 NULL,
325 NULL,
326 NULL,
327 NULL,
328 NULL,
329 NULL,
330 NULL,
331 NULL,
332 NULL,
333 NULL,
334 "hsdiv3_16fft_main_4_hsdivout2_clk",
335 "hsdiv3_16fft_main_15_hsdivout2_clk",
336 NULL,
337 NULL,
338 "board_0_audio_ext_refclk1_out",
339};
340
341static const char * const mcasp_ahclko_mux_out2_parents[] = {
342 NULL,
343 NULL,
344 NULL,
345 NULL,
346 NULL,
347 NULL,
348 NULL,
349 NULL,
350 NULL,
351 NULL,
352 NULL,
353 NULL,
354 NULL,
355 NULL,
356 NULL,
357 NULL,
358 NULL,
359 NULL,
360 NULL,
361 NULL,
362 NULL,
363 NULL,
364 NULL,
365 NULL,
366 NULL,
367 NULL,
368 NULL,
369 NULL,
370 "hsdiv3_16fft_main_4_hsdivout2_clk",
371 "hsdiv3_16fft_main_15_hsdivout2_clk",
372 NULL,
373 NULL,
374 "board_0_audio_ext_refclk2_out",
375};
376
377static const char * const mcasp_ahclko_mux_out3_parents[] = {
378 NULL,
379 NULL,
380 NULL,
381 NULL,
382 NULL,
383 NULL,
384 NULL,
385 NULL,
386 NULL,
387 NULL,
388 NULL,
389 NULL,
390 NULL,
391 NULL,
392 NULL,
393 NULL,
394 NULL,
395 NULL,
396 NULL,
397 NULL,
398 NULL,
399 NULL,
400 NULL,
401 NULL,
402 NULL,
403 NULL,
404 NULL,
405 NULL,
406 "hsdiv3_16fft_main_4_hsdivout2_clk",
407 "hsdiv3_16fft_main_15_hsdivout2_clk",
408 NULL,
409 NULL,
410 "board_0_audio_ext_refclk3_out",
411};
412
413static const char * const obsclk0_mux_out0_parents[] = {
414 "hsdiv4_16fft_main_0_hsdivout0_clk",
415 "hsdiv4_16fft_main_1_hsdivout0_clk",
416 "hsdiv4_16fft_main_2_hsdivout0_clk",
417 "hsdiv4_16fft_main_3_hsdivout0_clk",
418 "hsdiv3_16fft_main_4_hsdivout0_clk",
419 "hsdiv3_16fft_main_5_hsdivout0_clk",
420 "hsdiv0_16fft_main_6_hsdivout0_clk",
421 NULL,
422 NULL,
423 NULL,
424 NULL,
425 NULL,
426 "hsdiv0_16fft_main_12_hsdivout0_clk",
427 "obsclk1_mux_out0",
428 "hsdiv1_16fft_main_14_hsdivout0_clk",
429 "hsdiv3_16fft_main_15_hsdivout0_clk",
430 "hsdiv1_16fft_main_16_hsdivout0_clk",
431 "hsdiv1_16fft_main_17_hsdivout0_clk",
432 "hsdiv1_16fft_main_18_hsdivout0_clk",
433 "hsdiv1_16fft_main_19_hsdivout0_clk",
434 NULL,
435 NULL,
436 NULL,
437 "hsdiv1_16fft_main_23_hsdivout0_clk",
438 "hsdiv0_16fft_main_24_hsdivout0_clk",
439 "hsdiv1_16fft_main_25_hsdivout0_clk",
440 NULL,
441 "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
442 "gluelogic_lpxosc_clkout",
443 "hsdiv4_16fft_main_0_hsdivout0_clk",
444 "board_0_hfosc1_clk_out",
445 "gluelogic_hfosc0_clkout",
446};
447
448static const struct clk_data clk_list[] = {
449 CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
450 CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
451 CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
452 CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
453 CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
454 CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
455 CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
456 CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
457 CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
458 CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
459 CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
460 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
461 CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
462 CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
463 CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
464 CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
465 CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
466 CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
467 CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
468 CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
469 CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
470 CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]471 CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
472 CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]473 CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
474 CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
475 CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]476 CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
477 CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
478 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
479 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
480 CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]481 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]482 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]483 CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
484 CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
485 CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
486 CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
487 CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0),
488 CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0),
489 CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
490 CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
491 CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0),
492 CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
493 CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0),
494 CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0),
495 CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0),
496 CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0),
497 CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
498 CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
499 CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0),
500 CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
501 CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
502 CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0),
503 CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0),
504 CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
505 CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
506 CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
507 CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0),
508 CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0),
509 CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0),
510 CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0),
511 CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0),
512 CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
513 CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
514 CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
515 CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
516 CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0),
517 CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0),
518 CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
519 CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
520 CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]521 CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
522 CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
523 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0),
524 CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0),
525 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
526 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
527 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0),
528 CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]529 CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
530 CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]531 CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
532 CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]533 CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0),
534 CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
535 CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0),
536 CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0),
537 CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0),
538 CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
539 CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
540 CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0),
541 CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0),
542 CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
543 CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0),
544 CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0),
545 CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
546 CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
547 CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]548 CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
549 CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]550 CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
551 CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0),
552 CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0),
553 CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
554 CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]555 CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
556 CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
557 CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0),
558 CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
559 CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
560 CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0),
561 CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0, 0),
562 CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0, 0),
563 CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0, 0),
564 CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
565 CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0, 0),
566 CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0, 0),
567 CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0, 0),
568 CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0, 0),
569 CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
570 CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
571 CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
572 CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
573 CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
574 CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0),
575 CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
576 CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
577 CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0),
578 CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
579 CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]580 CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]581 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
582 CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]583 CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
584 CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
585 CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0),
586 CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
587 CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
588 CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
589 CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
590 CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
591 CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]592 CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0, 0),
593 CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
594 CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0, 0),
595 CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0),
596 CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]597 CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0),
598 CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0),
599 CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0),
600 CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0),
601 CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
Suman Annadb4c2dc2021-09-07 17:16:58 -0500[diff] [blame]602 CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0),
603 CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
604 CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
Dave Gerlach6bf97552021-06-11 11:45:18 +0300[diff] [blame]605};
606
607static const struct dev_clk soc_dev_clk_data[] = {
608 DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
609 DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
610 DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
611 DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
612 DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
613 DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
614 DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
615 DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
616 DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
617 DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
618 DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
619 DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
620 DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
621 DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
622 DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
623 DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"),
624 DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
625 DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"),
626 DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
627 DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
628 DEV_CLK(61, 1, "gtc_clk_mux_out0"),
629 DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
630 DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
631 DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
632 DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
633 DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
634 DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
635 DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
636 DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
637 DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
638 DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"),
639 DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
640 DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
641 DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
642 DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
643 DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"),
644 DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
645 DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"),
646 DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"),
647 DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"),
648 DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
649 DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
650 DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
651 DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
652 DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
653 DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
654 DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
655 DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
656 DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
657 DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
658 DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
659 DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"),
660 DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"),
661 DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
662 DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
663 DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"),
664 DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"),
665 DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
666 DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
667 DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
668 DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"),
669 DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"),
670 DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
671 DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
672 DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"),
673 DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
674 DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
675 DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
676 DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
677 DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
678 DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
679 DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
680 DEV_CLK(149, 0, "mcuusart_clk_sel_out0"),
681 DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
682 DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
683 DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
684 DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
685 DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
686 DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
687 DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
688 DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
689 DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
690 DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
691 DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"),
692 DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
693 DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
694 DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"),
695 DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"),
696 DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
697 DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
698 DEV_CLK(157, 104, "gpmc_fclk_sel_out0"),
699 DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"),
700 DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"),
701 DEV_CLK(157, 113, "osbclk0_div_out0"),
702 DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"),
703 DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"),
704 DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"),
705 DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"),
706 DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"),
707 DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"),
708 DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"),
709 DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"),
710 DEV_CLK(157, 127, "obsclk1_mux_out0"),
711 DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"),
712 DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"),
713 DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"),
714 DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"),
715 DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"),
716 DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"),
717 DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"),
718 DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"),
719 DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"),
720 DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
721 DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"),
722 DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"),
723 DEV_CLK(157, 144, "board_0_hfosc1_clk_out"),
724 DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"),
725 DEV_CLK(157, 146, "obsclk1_mux_out0"),
726 DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"),
727 DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"),
728 DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"),
729 DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"),
730 DEV_CLK(157, 153, "mcu_obsclk_div_out0"),
731 DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"),
732 DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
733 DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
734 DEV_CLK(157, 172, "clkout_mux_out0"),
735 DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"),
736 DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"),
737 DEV_CLK(157, 175, "mcu_clkout_mux_out0"),
738 DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
739 DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
740 DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"),
741 DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"),
742 DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"),
743 DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"),
744 DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"),
745 DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"),
746 DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"),
747 DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"),
748 DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"),
749 DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"),
750 DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"),
751 DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"),
752 DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"),
753 DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"),
754 DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"),
755 DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"),
756 DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"),
757 DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
758 DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"),
759 DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"),
760 DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
761 DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
762 DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
763 DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
764 DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
765 DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
766 DEV_CLK(288, 15, "usb0_refclk_sel_out0"),
767 DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"),
768 DEV_CLK(288, 17, "board_0_hfosc1_clk_out"),
769 DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
770 DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
771 DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
772 DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
773 DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
774 DEV_CLK(289, 15, "usb1_refclk_sel_out0"),
775 DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"),
776 DEV_CLK(289, 17, "board_0_hfosc1_clk_out"),
777 DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
778 DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
779};
780
781const struct ti_k3_clk_platdata j721e_clk_platdata = {
782 .clk_list = clk_list,
783 .clk_list_cnt = 156,
784 .soc_dev_clk_data = soc_dev_clk_data,
785 .soc_dev_clk_data_cnt = 171,
786};