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git01.mediatek.com / filogic / uboot / d0f8b69257e214e8041f39ce2107968a038f362b / . / include / configs / sama5d3xek.h
blob: f61b6e0dabc7d2315ba881e6dab29ee4e3a7647e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]2/*
3 * Configuation settings for the SAMA5D3xEK board.
4 *
5 * Copyright (C) 2012 - 2013 Atmel
6 *
7 * based on at91sam9m10g45ek.h by:
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]15#include "at91-sama5_common.h"
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]16
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]17/*
18 * This needs to be defined for the OHCI code to work but it is defined as
19 * ATMEL_ID_UHPHS in the CPU specific header files.
20 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]21#define ATMEL_ID_UHP 32
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]22
23/*
24 * Specify the clock enable bit in the PMC_SCER register.
25 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]26#define ATMEL_PMC_UHP (1 << 6)
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]27
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]28/* board specific (not enough SRAM) */
29#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
30
Bo Shenb15f4f62014-07-18 16:43:08 +0800[diff] [blame]31/* NOR flash */
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]32#ifdef CONFIG_MTD_NOR_FLASH
Bo Shenb15f4f62014-07-18 16:43:08 +0800[diff] [blame]33#define CONFIG_SYS_FLASH_BASE 0x10000000
34#define CONFIG_SYS_MAX_FLASH_SECT 131
Bo Shenb15f4f62014-07-18 16:43:08 +0800[diff] [blame]35#endif
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]36
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]37/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]38#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]39#define CONFIG_SYS_SDRAM_SIZE 0x20000000
40
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]41/* SerialFlash */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]42
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]43/* NAND flash */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]44#ifdef CONFIG_CMD_NAND
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]45#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]46#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]47/* our ALE is AD21 */
48#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
49/* our CLE is AD22 */
50#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]51#endif
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]52
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]53/* USB */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]54#ifdef CONFIG_CMD_USB
Bo Shen4a985df2013-10-21 16:14:00 +0800[diff] [blame]55#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]56#define CONFIG_USB_OHCI_NEW
57#define CONFIG_SYS_USB_OHCI_CPU_INIT
58#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
59#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
60#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]61#endif
62
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]63/* SPL */
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]64
Bo Shen37a36b32014-03-03 14:47:15 +0800[diff] [blame]65#define CONFIG_SYS_MONITOR_LEN (512 << 10)
66
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]67#endif