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Phil Edworthy2b3228d2011-06-01 07:35:13 +01001/*
Phil Edworthy958b7542011-06-09 16:22:43 +01002 * Configuation settings for the Renesas RSK2+SH7264 board
Phil Edworthy2b3228d2011-06-01 07:35:13 +01003 *
4 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Phil Edworthy2b3228d2011-06-01 07:35:13 +01009 */
10
11#ifndef __RSK7264_H
12#define __RSK7264_H
13
Phil Edworthy2b3228d2011-06-01 07:35:13 +010014#define CONFIG_CPU_SH7264 1
Phil Edworthy958b7542011-06-09 16:22:43 +010015#define CONFIG_RSK7264 1
Phil Edworthy2b3228d2011-06-01 07:35:13 +010016
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
18
Phil Edworthy958b7542011-06-09 16:22:43 +010019#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
Phil Edworthy2b3228d2011-06-01 07:35:13 +010020
Phil Edworthy958b7542011-06-09 16:22:43 +010021#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010022#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
23#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
24#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010025
Phil Edworthy958b7542011-06-09 16:22:43 +010026/* Serial */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010027#define CONFIG_CONS_SCIF3 1
28
Phil Edworthy958b7542011-06-09 16:22:43 +010029/* Memory */
30/* u-boot relocated to top 256KB of ram */
31#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
32#define CONFIG_SYS_SDRAM_BASE 0x0C000000
Phil Edworthy2b3228d2011-06-01 07:35:13 +010033#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
34
Phil Edworthy958b7542011-06-09 16:22:43 +010035#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
36#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010037#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Phil Edworthy958b7542011-06-09 16:22:43 +010038#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
39#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010040
Phil Edworthy958b7542011-06-09 16:22:43 +010041/* Flash */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010042#define CONFIG_FLASH_CFI_DRIVER
43#define CONFIG_SYS_FLASH_CFI
44#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Phil Edworthy958b7542011-06-09 16:22:43 +010045#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010046#define CONFIG_SYS_MAX_FLASH_BANKS 1
Phil Edworthy958b7542011-06-09 16:22:43 +010047#define CONFIG_SYS_MAX_FLASH_SECT 512
Phil Edworthy2b3228d2011-06-01 07:35:13 +010048
Phil Edworthy958b7542011-06-09 16:22:43 +010049#define CONFIG_ENV_OFFSET (128 * 1024)
50#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010051#define CONFIG_ENV_SECT_SIZE (128 * 1024)
52#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Phil Edworthy2b3228d2011-06-01 07:35:13 +010053
54/* Board Clock */
Phil Edworthyf701b5e2012-02-13 02:03:50 +000055#define CONFIG_SYS_CLK_FREQ 36000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090056#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
57#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthy958b7542011-06-09 16:22:43 +010058#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsubefb5cc2014-01-08 14:57:30 +090059#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy2b3228d2011-06-01 07:35:13 +010060
61/* Network interface */
Phil Edworthy2b3228d2011-06-01 07:35:13 +010062#define CONFIG_SMC911X
63#define CONFIG_SMC911X_16_BIT
Phil Edworthy958b7542011-06-09 16:22:43 +010064#define CONFIG_SMC911X_BASE 0x28000000
Phil Edworthy2b3228d2011-06-01 07:35:13 +010065
66#endif /* __RSK7264_H */