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git01.mediatek.com / filogic / uboot / d0d3e5e268ef05b6b070853e1e8de0c4844afc99 / . / arch / arm / dts / k3-am65-mcu.dtsi
blob: bc9a87210da995a98e3e9e6ba5924b10c17da971 [file] [log] [blame]
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
Suman Anna34721e52019-09-04 16:01:41 +0530[diff] [blame]5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]6 */
7
8&cbass_mcu {
9 mcu_uart0: serial@40a00000 {
10 compatible = "ti,am654-uart";
11 reg = <0x00 0x40a00000 0x00 0x100>;
12 reg-shift = <2>;
13 reg-io-width = <4>;
14 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
15 clock-frequency = <96000000>;
16 current-speed = <115200>;
17 };
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]18
19 mcu_i2c0: i2c@40b00000 {
20 compatible = "ti,am654-i2c", "ti,omap4-i2c";
21 reg = <0x0 0x40b00000 0x0 0x100>;
22 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
23 #address-cells = <1>;
24 #size-cells = <0>;
25 clock-names = "fck";
26 clocks = <&k3_clks 114 1>;
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]27 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]28 };
Suman Anna34721e52019-09-04 16:01:41 +0530[diff] [blame]29
30 mcu_r5fss0: r5fss@41000000 {
31 compatible = "ti,am654-r5fss";
32 lockstep-mode = <0>;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 ranges = <0x41000000 0x00 0x41000000 0x20000>,
36 <0x41400000 0x00 0x41400000 0x20000>;
37 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
38
39 mcu_r5fss0_core0: r5f@41000000 {
40 compatible = "ti,am654-r5f";
41 reg = <0x41000000 0x00008000>,
42 <0x41010000 0x00008000>;
43 reg-names = "atcm", "btcm";
44 ti,sci = <&dmsc>;
45 ti,sci-dev-id = <159>;
46 ti,sci-proc-ids = <0x01 0xFF>;
47 resets = <&k3_reset 159 1>;
48 atcm-enable = <1>;
49 btcm-enable = <1>;
50 loczrama = <1>;
51 };
52
53 mcu_r5fss0_core1: r5f@41400000 {
54 compatible = "ti,am654-r5f";
55 reg = <0x41400000 0x00008000>,
56 <0x41410000 0x00008000>;
57 reg-names = "atcm", "btcm";
58 ti,sci = <&dmsc>;
59 ti,sci-dev-id = <245>;
60 ti,sci-proc-ids = <0x02 0xFF>;
61 resets = <&k3_reset 245 1>;
62 atcm-enable = <1>;
63 btcm-enable = <1>;
64 loczrama = <1>;
65 };
66 };
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]67
68 fss: fss@47000000 {
69 compatible = "simple-bus";
70 #address-cells = <2>;
71 #size-cells = <2>;
72 ranges;
73
74 ospi0: spi@47040000 {
75 compatible = "ti,am654-ospi", "cdns,qspi-nor";
76 reg = <0x0 0x47040000 0x0 0x100>,
77 <0x5 0x00000000 0x1 0x0000000>;
78 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
79 cdns,fifo-depth = <256>;
80 cdns,fifo-width = <4>;
81 cdns,trigger-address = <0x0>;
82 clocks = <&k3_clks 248 0>;
83 assigned-clocks = <&k3_clks 248 0>;
84 assigned-clock-parents = <&k3_clks 248 2>;
85 assigned-clock-rates = <166666666>;
86 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90
91 ospi1: spi@47050000 {
92 compatible = "ti,am654-ospi", "cdns,qspi-nor";
93 reg = <0x0 0x47050000 0x0 0x100>,
94 <0x7 0x00000000 0x1 0x00000000>;
95 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
96 cdns,fifo-depth = <256>;
97 cdns,fifo-width = <4>;
98 cdns,trigger-address = <0x0>;
99 clocks = <&k3_clks 249 6>;
100 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 };
104 };
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]105};