| Simon Glass | c0b2ae5 | 2020-04-08 16:57:30 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2015-2017 Intel Corp. |
| 4 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
| 5 | * Copyright Google LLC 2019 |
| 6 | * |
| 7 | * Modified from coreboot apollolake/include/soc/nvs.h |
| 8 | */ |
| 9 | |
| 10 | #ifndef _GLOBAL_NVS_H_ |
| 11 | #define _GLOBAL_NVS_H_ |
| 12 | |
| 13 | struct __packed acpi_global_nvs { |
| 14 | /* Miscellaneous */ |
| 15 | u8 pcnt; /* 0x00 - Processor Count */ |
| 16 | u8 ppcm; /* 0x01 - Max PPC State */ |
| 17 | u8 lids; /* 0x02 - LID State */ |
| 18 | u8 pwrs; /* 0x03 - AC Power State */ |
| 19 | u8 dpte; /* 0x04 - Enable DPTF */ |
| 20 | u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */ |
| 21 | u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ |
| 22 | u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ |
| 23 | u64 nhla; /* 0x19 - 0x20 - NHLT Address */ |
| 24 | u32 nhll; /* 0x21 - 0x24 - NHLT Length */ |
| 25 | u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ |
| 26 | u8 scdp; /* 0x29 - SD_CD GPIO portid */ |
| 27 | u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ |
| 28 | u8 uior; /* 0x2b - UART debug controller init on S3 resume */ |
| 29 | u8 ecps; /* 0x2c - SGX Enabled status */ |
| 30 | u64 emna; /* 0x2d - 0x34 EPC base address */ |
| 31 | u64 elng; /* 0x35 - 0x3c EPC Length */ |
| 32 | u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ |
| 33 | u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ |
| 34 | }; |
| 35 | |
| 36 | #endif /* _GLOBAL_NVS_H_ */ |