| Bryan Wu | e956f34 | 2009-12-16 22:04:02 -0500 | [diff] [blame] | 1 | /* |
| 2 | * USB Masks |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_USB__ |
| 6 | #define __BFIN_PERIPHERAL_USB__ |
| 7 | |
| 8 | /* Bit masks for USB_FADDR */ |
| 9 | |
| 10 | #define FUNCTION_ADDRESS 0x7f /* Function address */ |
| 11 | |
| 12 | /* Bit masks for USB_POWER */ |
| 13 | |
| 14 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ |
| 15 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ |
| 16 | #define RESUME_MODE 0x4 /* DMA Mode */ |
| 17 | #define RESET 0x8 /* Reset indicator */ |
| 18 | #define HS_MODE 0x10 /* High Speed mode indicator */ |
| 19 | #define HS_ENABLE 0x20 /* high Speed Enable */ |
| 20 | #define SOFT_CONN 0x40 /* Soft connect */ |
| 21 | #define ISO_UPDATE 0x80 /* Isochronous update */ |
| 22 | |
| 23 | /* Bit masks for USB_INTRTX */ |
| 24 | |
| 25 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ |
| 26 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ |
| 27 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ |
| 28 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ |
| 29 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ |
| 30 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ |
| 31 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ |
| 32 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ |
| 33 | |
| 34 | /* Bit masks for USB_INTRRX */ |
| 35 | |
| 36 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ |
| 37 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ |
| 38 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ |
| 39 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ |
| 40 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ |
| 41 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ |
| 42 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ |
| 43 | |
| 44 | /* Bit masks for USB_INTRTXE */ |
| 45 | |
| 46 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ |
| 47 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt enable */ |
| 48 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt enable */ |
| 49 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt enable */ |
| 50 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt enable */ |
| 51 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt enable */ |
| 52 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt enable */ |
| 53 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt enable */ |
| 54 | |
| 55 | /* Bit masks for USB_INTRRXE */ |
| 56 | |
| 57 | #define EP1_RX_E 0x02 /* Rx Endpoint 1 interrupt enable */ |
| 58 | #define EP2_RX_E 0x04 /* Rx Endpoint 2 interrupt enable */ |
| 59 | #define EP3_RX_E 0x08 /* Rx Endpoint 3 interrupt enable */ |
| 60 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt enable */ |
| 61 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt enable */ |
| 62 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt enable */ |
| 63 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt enable */ |
| 64 | |
| 65 | /* Bit masks for USB_INTRUSB */ |
| 66 | |
| 67 | #define SUSPEND_B 0x01 /* Suspend indicator */ |
| 68 | #define RESUME_B 0x02 /* Resume indicator */ |
| 69 | #define RESET_OR_BABLE_B 0x04 /* Reset/babble indicator */ |
| 70 | #define SOF_B 0x08 /* Start of frame */ |
| 71 | #define CONN_B 0x10 /* Connection indicator */ |
| 72 | #define DISCON_B 0x20 /* Disconnect indicator */ |
| 73 | #define SESSION_REQ_B 0x40 /* Session Request */ |
| 74 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ |
| 75 | |
| 76 | /* Bit masks for USB_INTRUSBE */ |
| 77 | |
| 78 | #define SUSPEND_BE 0x01 /* Suspend indicator int enable */ |
| 79 | #define RESUME_BE 0x02 /* Resume indicator int enable */ |
| 80 | #define RESET_OR_BABLE_BE 0x04 /* Reset/babble indicator int enable */ |
| 81 | #define SOF_BE 0x08 /* Start of frame int enable */ |
| 82 | #define CONN_BE 0x10 /* Connection indicator int enable */ |
| 83 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ |
| 84 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ |
| 85 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ |
| 86 | |
| 87 | /* Bit masks for USB_FRAME */ |
| 88 | |
| 89 | #define FRAME_NUMBER 0x7ff /* Frame number */ |
| 90 | |
| 91 | /* Bit masks for USB_INDEX */ |
| 92 | |
| 93 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ |
| 94 | |
| 95 | /* Bit masks for USB_GLOBAL_CTL */ |
| 96 | |
| 97 | #define GLOBAL_ENA 0x0001 /* enables USB module */ |
| 98 | #define EP1_TX_ENA 0x0002 /* Transmit endpoint 1 enable */ |
| 99 | #define EP2_TX_ENA 0x0004 /* Transmit endpoint 2 enable */ |
| 100 | #define EP3_TX_ENA 0x0008 /* Transmit endpoint 3 enable */ |
| 101 | #define EP4_TX_ENA 0x0010 /* Transmit endpoint 4 enable */ |
| 102 | #define EP5_TX_ENA 0x0020 /* Transmit endpoint 5 enable */ |
| 103 | #define EP6_TX_ENA 0x0040 /* Transmit endpoint 6 enable */ |
| 104 | #define EP7_TX_ENA 0x0080 /* Transmit endpoint 7 enable */ |
| 105 | #define EP1_RX_ENA 0x0100 /* Receive endpoint 1 enable */ |
| 106 | #define EP2_RX_ENA 0x0200 /* Receive endpoint 2 enable */ |
| 107 | #define EP3_RX_ENA 0x0400 /* Receive endpoint 3 enable */ |
| 108 | #define EP4_RX_ENA 0x0800 /* Receive endpoint 4 enable */ |
| 109 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ |
| 110 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ |
| 111 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ |
| 112 | |
| 113 | /* Bit masks for USB_OTG_DEV_CTL */ |
| 114 | |
| 115 | #define SESSION 0x1 /* session indicator */ |
| 116 | #define HOST_REQ 0x2 /* Host negotiation request */ |
| 117 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ |
| 118 | #define VBUS0 0x8 /* Vbus level indicator[0] */ |
| 119 | #define VBUS1 0x10 /* Vbus level indicator[1] */ |
| 120 | #define LSDEV 0x20 /* Low-speed indicator */ |
| 121 | #define FSDEV 0x40 /* Full or High-speed indicator */ |
| 122 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ |
| 123 | |
| 124 | /* Bit masks for USB_OTG_VBUS_IRQ */ |
| 125 | |
| 126 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ |
| 127 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ |
| 128 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ |
| 129 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ |
| 130 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ |
| 131 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ |
| 132 | |
| 133 | /* Bit masks for USB_OTG_VBUS_MASK */ |
| 134 | |
| 135 | #define DRIVE_VBUS_ON_ENA 0x01 /* enable DRIVE_VBUS_ON interrupt */ |
| 136 | #define DRIVE_VBUS_OFF_ENA 0x02 /* enable DRIVE_VBUS_OFF interrupt */ |
| 137 | #define CHRG_VBUS_START_ENA 0x04 /* enable CHRG_VBUS_START interrupt */ |
| 138 | #define CHRG_VBUS_END_ENA 0x08 /* enable CHRG_VBUS_END interrupt */ |
| 139 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ |
| 140 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ |
| 141 | |
| 142 | /* Bit masks for USB_CSR0 */ |
| 143 | |
| 144 | #define RXPKTRDY 0x1 /* data packet receive indicator */ |
| 145 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ |
| 146 | #define STALL_SENT 0x4 /* STALL handshake sent */ |
| 147 | #define DATAEND 0x8 /* Data end indicator */ |
| 148 | #define SETUPEND 0x10 /* Setup end */ |
| 149 | #define SENDSTALL 0x20 /* Send STALL handshake */ |
| 150 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ |
| 151 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ |
| 152 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ |
| 153 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ |
| 154 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ |
| 155 | #define ERROR_H 0x10 /* timeout error indicator host mode */ |
| 156 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ |
| 157 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ |
| 158 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ |
| 159 | |
| 160 | /* Bit masks for USB_COUNT0 */ |
| 161 | |
| 162 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ |
| 163 | |
| 164 | /* Bit masks for USB_NAKLIMIT0 */ |
| 165 | |
| 166 | #define EP0_NAK_LIMIT 0x1f /* frames/micro frames count after which EP0 timeouts */ |
| 167 | |
| 168 | /* Bit masks for USB_TX_MAX_PACKET */ |
| 169 | |
| 170 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ |
| 171 | |
| 172 | /* Bit masks for USB_RX_MAX_PACKET */ |
| 173 | |
| 174 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ |
| 175 | |
| 176 | /* Bit masks for USB_TXCSR */ |
| 177 | |
| 178 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ |
| 179 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ |
| 180 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ |
| 181 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ |
| 182 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ |
| 183 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ |
| 184 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ |
| 185 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ |
| 186 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ |
| 187 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ |
| 188 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ |
| 189 | #define ISO_T 0x4000 /* enable Isochronous transfers */ |
| 190 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ |
| 191 | #define ERROR_TH 0x4 /* error condition host mode */ |
| 192 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ |
| 193 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ |
| 194 | |
| 195 | /* Bit masks for USB_TXCOUNT */ |
| 196 | |
| 197 | #define TX_COUNT 0x1fff /* Byte len for the selected endpoint Tx FIFO */ |
| 198 | |
| 199 | /* Bit masks for USB_RXCSR */ |
| 200 | |
| 201 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ |
| 202 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ |
| 203 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ |
| 204 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ |
| 205 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ |
| 206 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ |
| 207 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ |
| 208 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ |
| 209 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ |
| 210 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ |
| 211 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ |
| 212 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ |
| 213 | #define ISO_R 0x4000 /* enable Isochronous transfers */ |
| 214 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ |
| 215 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ |
| 216 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ |
| 217 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ |
| 218 | #define INCOMPRX_RH 0x100 /* large packet is split host mode */ |
| 219 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ |
| 220 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ |
| 221 | |
| 222 | /* Bit masks for USB_RXCOUNT */ |
| 223 | |
| 224 | #define RX_COUNT 0x1fff /* Packet byte len in the Rx FIFO */ |
| 225 | |
| 226 | /* Bit masks for USB_TXTYPE */ |
| 227 | |
| 228 | #define TARGET_EP_NO_T 0xf /* EP number */ |
| 229 | #define PROTOCOL_T 0xc /* transfer type */ |
| 230 | |
| 231 | /* Bit masks for USB_TXINTERVAL */ |
| 232 | |
| 233 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ |
| 234 | |
| 235 | /* Bit masks for USB_RXTYPE */ |
| 236 | |
| 237 | #define TARGET_EP_NO_R 0xf /* EP number */ |
| 238 | #define PROTOCOL_R 0xc /* transfer type */ |
| 239 | |
| 240 | /* Bit masks for USB_RXINTERVAL */ |
| 241 | |
| 242 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ |
| 243 | |
| 244 | /* Bit masks for USB_DMA_INTERRUPT */ |
| 245 | |
| 246 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ |
| 247 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ |
| 248 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ |
| 249 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ |
| 250 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ |
| 251 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ |
| 252 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ |
| 253 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ |
| 254 | |
| 255 | /* Bit masks for USB_DMAxCONTROL */ |
| 256 | |
| 257 | #define DMA_ENA 0x1 /* DMA enable */ |
| 258 | #define DIRECTION 0x2 /* direction of DMA transfer */ |
| 259 | #define MODE 0x4 /* DMA Bus error */ |
| 260 | #define INT_ENA 0x8 /* Interrupt enable */ |
| 261 | #define EPNUM 0xf0 /* EP number */ |
| 262 | #define BUSERROR 0x100 /* DMA Bus error */ |
| 263 | |
| 264 | #endif |