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git01.mediatek.com / filogic / uboot / d031b9e08bde651178e2e6693ed300cec1b0e2a2 / . / arch / arm / dts / vf.dtsi
blob: 477d8de2d49b241488366bb4f85fd2b080d4d548 [file] [log] [blame]
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+ or X11
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]5 */
6/include/ "skeleton.dtsi"
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]7#include <dt-bindings/gpio/gpio.h>
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]8
9/ {
10 aliases {
11 gpio0 = &gpio0;
12 gpio1 = &gpio1;
13 gpio2 = &gpio2;
14 gpio3 = &gpio3;
15 gpio4 = &gpio4;
Bhuvanchandra DV263d4702016-01-27 10:31:45 +0530[diff] [blame]16 serial0 = &uart0;
17 serial1 = &uart1;
18 serial2 = &uart2;
19 serial3 = &uart3;
20 serial4 = &uart4;
21 serial5 = &uart5;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]22 spi0 = &dspi0;
23 spi1 = &dspi1;
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]24 ehci0 = &ehci0;
25 ehci1 = &ehci1;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]26 };
27
28 soc {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 ranges;
33
34 aips0: aips-bus@40000000 {
35 compatible = "fsl,aips-bus", "simple-bus";
36 #address-cells = <1>;
37 #size-cells = <1>;
Stefan Agner08afbfe2016-11-30 13:41:57 -0800[diff] [blame]38 reg = <0x40000000 0x00070000>;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]39 ranges;
40
Bhuvanchandra DV263d4702016-01-27 10:31:45 +0530[diff] [blame]41 uart0: serial@40027000 {
42 compatible = "fsl,vf610-lpuart";
43 reg = <0x40027000 0x1000>;
44 status = "disabled";
45 };
46
47 uart1: serial@40028000 {
48 compatible = "fsl,vf610-lpuart";
49 reg = <0x40028000 0x1000>;
50 status = "disabled";
51 };
52
53 uart2: serial@40029000 {
54 compatible = "fsl,vf610-lpuart";
55 reg = <0x40029000 0x1000>;
56 status = "disabled";
57 };
58
59 uart3: serial@4002a000 {
60 compatible = "fsl,vf610-lpuart";
61 reg = <0x4002a000 0x1000>;
62 status = "disabled";
63 };
64
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]65 dspi0: dspi0@4002c000 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "fsl,vf610-dspi";
69 reg = <0x4002c000 0x1000>;
70 num-cs = <5>;
71 status = "disabled";
72 };
73
74 dspi1: dspi1@4002d000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "fsl,vf610-dspi";
78 reg = <0x4002d000 0x1000>;
79 num-cs = <5>;
80 status = "disabled";
81 };
82
83 qspi0: quadspi@40044000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 compatible = "fsl,vf610-qspi";
Albert ARIBAUD \(3ADEV\)ddef3b62016-09-26 09:08:08 +0200[diff] [blame]87 reg = <0x40044000 0x1000>,
88 <0x20000000 0x10000000>;
89 reg-names = "QuadSPI", "QuadSPI-memory";
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]90 status = "disabled";
91 };
92
93 gpio0: gpio@40049000 {
94 compatible = "fsl,vf610-gpio";
95 reg = <0x400ff000 0x40>;
96 #gpio-cells = <2>;
97 };
98
99 gpio1: gpio@4004a000 {
100 compatible = "fsl,vf610-gpio";
101 reg = <0x400ff040 0x40>;
102 #gpio-cells = <2>;
103 };
104
105 gpio2: gpio@4004b000 {
106 compatible = "fsl,vf610-gpio";
107 reg = <0x400ff080 0x40>;
108 #gpio-cells = <2>;
109 };
110
111 gpio3: gpio@4004c000 {
112 compatible = "fsl,vf610-gpio";
113 reg = <0x400ff0c0 0x40>;
114 #gpio-cells = <2>;
115 };
116
117 gpio4: gpio@4004d000 {
118 compatible = "fsl,vf610-gpio";
119 reg = <0x400ff100 0x40>;
120 #gpio-cells = <2>;
121 };
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]122
123 ehci0: ehci@40034000 {
124 compatible = "fsl,vf610-usb";
125 reg = <0x40034000 0x800>;
126 status = "disabled";
127 };
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]128 };
129
130 aips1: aips-bus@40080000 {
131 compatible = "fsl,aips-bus", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
Stefan Agner08afbfe2016-11-30 13:41:57 -0800[diff] [blame]134 reg = <0x40080000 0x0007f000>;
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]135 ranges;
Bhuvanchandra DV263d4702016-01-27 10:31:45 +0530[diff] [blame]136
137 uart4: serial@400a9000 {
138 compatible = "fsl,vf610-lpuart";
139 reg = <0x400a9000 0x1000>;
140 status = "disabled";
141 };
142
143 uart5: serial@400aa000 {
144 compatible = "fsl,vf610-lpuart";
145 reg = <0x400aa000 0x1000>;
146 status = "disabled";
147 };
148
Sanchayan Maity05fb4b92016-08-09 23:45:00 +0530[diff] [blame]149 ehci1: ehci@400b4000 {
150 compatible = "fsl,vf610-usb";
151 reg = <0x400b4000 0x800>;
152 status = "disabled";
153 };
Bhuvanchandra DV599b3b62015-06-01 18:37:21 +0530[diff] [blame]154 };
155 };
156};