dts/upstream/src/arm64/sprd/sharkl3.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Unisoc Sharkl3 platform DTS file
 *
 * Copyright (C) 2019, Unisoc Inc.
 */

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ap_ahb_regs: syscon@20e00000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x20e00000 0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x20e00000 0x4000>;

			apahb_gate: apahb-gate@0 {
				compatible = "sprd,sc9863a-apahb-gate";
				reg = <0x0 0x1020>;
				#clock-cells = <1>;
			};
		};

		pmu_regs: syscon@402b0000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x402b0000 0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x402b0000 0x4000>;

			pmu_gate: pmu-gate@0 {
				compatible = "sprd,sc9863a-pmu-gate";
				reg = <0 0x1200>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		aon_apb_regs: syscon@402e0000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x402e0000 0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x402e0000 0x4000>;

			aonapb_gate: aonapb-gate@0 {
				compatible = "sprd,sc9863a-aonapb-gate";
				reg = <0 0x1100>;
				#clock-cells = <1>;
			};
		};

		anlg_phy_g2_regs: syscon@40353000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x40353000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x40353000 0x3000>;

			pll: pll@0 {
				compatible = "sprd,sc9863a-pll";
				reg = <0 0x100>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		anlg_phy_g4_regs: syscon@40359000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x40359000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x40359000 0x3000>;

			mpll: mpll@0 {
				compatible = "sprd,sc9863a-mpll";
				reg = <0 0x100>;
				#clock-cells = <1>;
			};
		};

		anlg_phy_g5_regs: syscon@4035c000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x4035c000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x4035c000 0x3000>;

			rpll: rpll@0 {
				compatible = "sprd,sc9863a-rpll";
				reg = <0 0x100>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		anlg_phy_g7_regs: syscon@40363000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x40363000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x40363000 0x3000>;

			dpll: dpll@0 {
				compatible = "sprd,sc9863a-dpll";
				reg = <0 0x100>;
				#clock-cells = <1>;
			};
		};

		mm_ahb_regs: syscon@60800000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x60800000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x60800000 0x3000>;

			mm_gate: mm-gate@0 {
				compatible = "sprd,sc9863a-mm-gate";
				reg = <0 0x1100>;
				#clock-cells = <1>;
			};
		};

		ap_apb_regs: syscon@71300000 {
			compatible = "sprd,sc9863a-glbregs", "syscon",
				     "simple-mfd";
			reg = <0 0x71300000 0 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x71300000 0x4000>;

			apapb_gate: apapb-gate@0 {
				compatible = "sprd,sc9863a-apapb-gate";
				reg = <0 0x1000>;
				clocks = <&ext_26m>;
				clock-names = "ext-26m";
				#clock-cells = <1>;
			};
		};

		apb@70000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0x70000000 0x10000000>;

			uart0: serial@0 {
				compatible = "sprd,sc9863a-uart",
					     "sprd,sc9836-uart";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};

			uart1: serial@100000 {
				compatible = "sprd,sc9863a-uart",
					     "sprd,sc9836-uart";
				reg = <0x100000 0x100>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};

			uart2: serial@200000 {
				compatible = "sprd,sc9863a-uart",
					     "sprd,sc9836-uart";
				reg = <0x200000 0x100>;
				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};

			uart3: serial@300000 {
				compatible = "sprd,sc9863a-uart",
					     "sprd,sc9836-uart";
				reg = <0x300000 0x100>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};

			uart4: serial@400000 {
				compatible = "sprd,sc9863a-uart",
					     "sprd,sc9836-uart";
				reg = <0x400000 0x100>;
				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ext_26m>;
				status = "disabled";
			};
		};
	};

	ext_26m: ext-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "ext-26m";
	};

	ext_32k: ext-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ext-32k";
	};

	ext_4m: ext-4m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <4000000>;
		clock-output-names = "ext-4m";
	};

	rco_100m: rco-100m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "rco-100m";
	};
};